Abstract: A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.

Abstract: A method of generating optimal input data for a design simulator providing output data related to output parameters in response to input data related to input parameters. The method includes; generating training data including sample input data and sample output data, selecting at least one essential input parameter affecting a plurality of output parameters from among the input parameters in accordance with an estimation model trained using the training data, and generating the optimal input data in accordance with essential input data corresponding to the at least one essential input parameter and the sample output data.

Abstract: An electronic device is provided. The electronic device includes a power receiver including a power receiving coil, a battery, and at least one processor operatively connected to the power receiver and the battery, wherein the at least one processor may be configured to identify whether a wireless charging protection mode has been entered, to wirelessly receive power in a first range from the power transmitting device through the power receiver when it is identified that a wireless charging protection mode has not been entered, to charge the battery using power in the first range, to identify a charge amount of the battery charged for a designated time, and to identify that a metallic foreign object exists, and to change the heat generation control condition in case it is identified that the charge amount of the battery is less than a designated value.

Abstract: According to certain embodiments, an electronic device comprises: a rechargeable battery configured to supply power to the electronic device; a processor connected to the battery; and memory storing a plurality of executable instructions, wherein the execution of the executable instructions by the processor causes performing a plurality of operations, wherein the plurality of operations comprises: charging the battery based on a target voltage level, wherein the target voltage level is based on a number of times the rechargeable battery has been previously charged, detecting that the voltage of the rechargeable battery is maintained within a range of levels lower than the target level, and protecting the battery in response to detecting.

Abstract: Disclosed are methods of predicting semiconductor material properties and methods of testing semiconductor devices using the same. The prediction method comprises preparing a machine learning model that is trained with a training system and using the machine learning model to predict material properties of a target system. The machine learning model is represented as a function of material properties with respect to a descriptor. The descriptor is calculated from unrelaxed charge density (UCD) that is represented by summation of atomic charge density (ACD) of single atoms.

Abstract: A method of generating a circuit model used to simulate an integrated circuit may include generating first feature element data and second feature element data by classifying feature data of a target semiconductor device according to measurement conditions, generating first target data and second target data by preprocessing the first feature element data and the second feature element data, respectively, generating a first machine learning model using the first target data and extracting a second machine learning model using the second target data, and generating the circuit model used to simulate the integrated circuit using the first machine learning model and the second machine learning model.

Abstract: According to an aspect of the present inventive concept, a simulation method for a semiconductor fabrication process includes obtaining, as input data, process parameters for controlling a semiconductor process of manufacturing semiconductor devices, or design parameters representing a structure of the semiconductor devices, or both the process parameters and the design parameters; generating predictive data for electrical characteristics of the semiconductor devices using a machine learning model based on the input data; generating reference data for the electrical characteristics of the semiconductor devices using a simulation tool based on the input data; and training the machine learning model using the predictive data and the reference data.

Abstract: Various embodiments of the present invention relate to an electronic device for diagnosing a battery, and the electronic device may include a battery; and a power management module operatively connected with the battery, and including a charging circuit which controls charge of the battery, wherein the power management module is configured to monitor a charge state of the battery, if the battery reaches a first designated state, identify a time taken to change from the first designated state to a second designated state, and determine whether the battery is abnormal, based at least in part on the identified time. Other various embodiments are possible.

Abstract: A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.

Abstract: A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

Abstract: A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

Abstract: A magnetic memory device can include an upper electrode, a lower electrode and a Magnetic Tunnel Junction (MTJ). The MTJ can include a reference magnetic pattern configured to generate a fixed magnetization and a free magnetic pattern on the reference magnetic pattern configured to generate a switchable magnetization that switches direction between parallel and anti-parallel to the fixed magnetization. A metal pattern can be on the free magnetic pattern and can be configured to conduct an in-plane current and a perpendicular-to-plane to/from the upper electrode.

Abstract: A magnetic memory device can include an upper electrode, a lower electrode and a Magnetic Tunnel Junction (MTJ). The MTJ can include a reference magnetic pattern configured to generate a fixed magnetization and a free magnetic pattern on the reference magnetic pattern configured to generate a switchable magnetization that switches direction between parallel and anti-parallel to the fixed magnetization. A metal pattern can be on the free magnetic pattern and can be configured to conduct an in-plane current and a perpendicular-to-plane to/from the upper electrode.