Abstract: The present invention provides methods for treating or ameliorating metabolic diseases, cholestatic liver diseases, or organ fibrosis, which comprises administering to a subject a therapeutically effective amount of a pharmaceutical composition comprising an isoxazole derivative, a racemate, an enantiomer, or a diastereoisomer thereof, or a pharmaceutically acceptable salt of the derivative, the racemate, the enantiomer, or the diastereoisomer.

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

Abstract: A camera module socket device for blocking a path through which foreign materials may ingress is provided. The camera module socket device having a camera module and a socket into which the camera module is inserted includes a cap for securing the camera module in the socket, and a buffer member for closure formed between a surface of the camera module and the cap to enclose the periphery of a lens portion of the camera module, thereby preventing malfunction of the camera module and image quality degradation due to ingress of foreign materials into the lens portion and absorbing shock forces exerted at the top of the camera module socket device.

Abstract: An impedance control circuit includes an impedance detector, an output driver and an impedance controller. The impedance detector generates a first output value to a detection pad connected between an external determination resistor and a pull-up transistor array, and outputs a second output value to a resistance divider terminal commonly connected between a pull-up and pull-down transistor array in response to a pull-up control code data and a pull-down control code data. The output driver has a commonly connected pull-up and pull-down transistor array, and a compensating unit connected to the pull-up and pull-down transistor array of the output driver, to compensate for quantization error of the pull-up and pull-down control code data. The impedance controller performs a comparison and counting operation so that the first and second output values of the impedance detector become approximated to a predetermined reference value, and generates the pull-up and pull-down control code data.

Abstract: A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohibition control unit for generating a transfer control signal to prohibit driving the transistors during a first time interval occurring when internal data transition, and applying the transfer control signal to the impedance matching array unit.

Abstract: A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.

Abstract: An impedance control circuit for use in a semiconductor device reduces an impedance mismatch between pull-up and pull-down resistances without increasing a resolution. The impedance control circuit includes an impedance detector, an output driver and an impedance controller. The impedance detector generates a first output value to a detection pad connected between an external determination resistor and a pull-up transistor array, and outputs a second output value to a resistance divider terminal commonly connected between a pull-up and pull-down transistor array in response to a pull-up control code data and a pull-down control code data. The output driver has a commonly connected pull-up and pull-down transistor array, and a compensating unit connected to the pull-up and pull-down transistor array of the output driver, to compensate for quantization error of the pull-up and pull-down control code data.

Abstract: A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohibition control unit for generating a transfer control signal to prohibit driving the transistors during a first time interval occurring when internal data transition, and applying the transfer control signal to the impedance matching array unit.

Abstract: A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.