Abstract: A semiconductor memory device may include banks. A sensor is disposed adjacent to the banks and configured to sense a temperature. An address buffer is configured to receive an address from an external device. A first demultiplexer is configured to transfer a row address in the address to one of the banks. A second demultiplexer is configured to transfer a column address in the address to one of the banks. A command buffer is configured to receive a command from the external device. A control logic block is configured to control the first and second demultiplexers and the banks in accordance with the command and bank information in the address. A data buffer is configured to exchange data signals between the banks and the external device. The control logic block may be further configured to transfer information on the temperature to the external device.

Abstract: A semiconductor memory device may include banks. A sensor is disposed adjacent to the banks and configured to sense a temperature. An address buffer is configured to receive an address from an external device. A first demultiplexer is configured to transfer a row address in the address to one of the banks. A second demultiplexer is configured to transfer a column address in the address to one of the banks. A command buffer is configured to receive a command from the external device. A control logic block is configured to control the first and second demultiplexers and the banks in accordance with the command and bank information in the address. A data buffer is configured to exchange data signals between the banks and the external device. The control logic block may be further configured to transfer information on the temperature to the external device.

Abstract: A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.

Abstract: A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.