Patents by Inventor Ji-Wang Lee
Ji-Wang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140286075Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.Type: ApplicationFiled: September 4, 2013Publication date: September 25, 2014Inventors: Akira KATAYAMA, Masahiro TAKAHASHI, Tsuneo INABA, Hyuck Sang YIM, Dong Keun KIM, Byoung Chan OH, Ji Wang LEE
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Publication number: 20140244930Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element configured to be changed in a resistance value according to a value of data stored therein; a first reference resistance element having a first resistance value; a second reference resistance element having a second resistance value larger than the first resistance value; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing inputs to the first input terminal and the second input terminal and inputs to the third input terminal and fourth input termiType: ApplicationFiled: October 18, 2013Publication date: August 28, 2014Applicant: SK hynix Inc.Inventor: Ji-Wang Lee
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Publication number: 20140241041Abstract: A reference column of a semiconductor memory includes a reference bit line; a reference source line; and first to Nth resistive memory cells disposed between the reference bit line and the reference source line. Data of a first state is stored in the first resistive memory cell and data of a second state is stored in the Nth resistive memory cell before a read operation, and the first and Nth resistive memory cells form current paths between the reference bit line and the reference source line in the read operation.Type: ApplicationFiled: February 26, 2014Publication date: August 28, 2014Applicant: SK HYNIX INC.Inventor: Ji-Wang Lee
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Patent number: 8610458Abstract: An impedance control circuit includes a first impedance unit configured to terminate an impedance node using an impedance value that is determined by an impedance control code, a second impedance unit configured to terminate the impedance node using an impedance value that is determined by an impedance control voltage, a comparison circuit configured to compare a voltage level of the impedance node and a voltage level of a reference voltage, generate an up/down signal indicating whether the voltage at the impedance node is greater than the reference voltage, and generate the impedance control voltage that has a voltage level corresponding to a difference between the voltage at the impedance node and the reference voltage, and a counter unit configured to increase or decrease a value of the impedance control code in response to the up/down signal.Type: GrantFiled: April 13, 2012Date of Patent: December 17, 2013Assignee: Hynix Semiconductor Inc.Inventor: Ji-Wang Lee
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Patent number: 8461878Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.Type: GrantFiled: November 19, 2012Date of Patent: June 11, 2013Assignee: SK Hynix Inc.Inventors: Ji-Wang Lee, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Jae-Min Jang, Chang-Kun Park
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Publication number: 20130113515Abstract: An impedance control circuit includes a first impedance unit configured to terminate an impedance node using an impedance value that is determined by an impedance control code, a second impedance unit configured to terminate the impedance node using an impedance value that is determined by an impedance control voltage, a comparison circuit configured to compare a voltage level of the impedance node and a voltage level of a reference voltage, generate an up/down signal indicating whether the voltage at the impedance node is greater than the reference voltage, and generate the impedance control voltage that has a voltage level corresponding to a difference between the voltage at the impedance node and the reference voltage, and a counter unit configured to increase or decrease a value of the impedance control code in response to the up/down signal.Type: ApplicationFiled: April 13, 2012Publication date: May 9, 2013Inventor: Ji-Wang LEE
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Patent number: 8436666Abstract: An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector.Type: GrantFiled: December 30, 2009Date of Patent: May 7, 2013Assignee: Hynix Semiconductor Inc.Inventors: Ji-Wang Lee, Yong-Ju Kim, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Jae-Min Jang, Chang-Kun Park
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Patent number: 8421530Abstract: A filter circuit includes a filtering unit configured to filter an input signal and generate an output signal, and a weight generation unit configured to monitor a variation of the output signal and generate weight information based on the monitored variation.Type: GrantFiled: April 1, 2011Date of Patent: April 16, 2013Assignee: Hynix Semiconductor Inc.Inventors: Ji-Wang Lee, Shin-Deok Kang
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Patent number: 8373456Abstract: The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.Type: GrantFiled: June 17, 2009Date of Patent: February 12, 2013Assignee: Hynix Semiconductor Inc.Inventors: Hae Rang Choi, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Ji Wang Lee, Jae Min Jang, Chang Kun Park
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Patent number: 8339159Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.Type: GrantFiled: August 13, 2009Date of Patent: December 25, 2012Assignee: Hynix Semiconductor Inc.Inventors: Ji-Wang Lee, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Jae-Min Jang, Chang-Kun Park
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Patent number: 8283804Abstract: A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.Type: GrantFiled: December 11, 2008Date of Patent: October 9, 2012Assignee: SK hynix Inc.Inventors: Hyung-Soo Kim, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
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Patent number: 8278981Abstract: A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.Type: GrantFiled: December 14, 2009Date of Patent: October 2, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hae-Rang Choi, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
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Patent number: 8270557Abstract: An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.Type: GrantFiled: December 29, 2010Date of Patent: September 18, 2012Assignee: Hynix Semiconductor Inc.Inventors: Ji-Wang Lee, Shin-Deok Kang
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Publication number: 20120161859Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator, and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.Type: ApplicationFiled: February 22, 2012Publication date: June 28, 2012Inventors: Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
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Publication number: 20120154030Abstract: A filter circuit includes a filtering unit configured to filter an input signal and generate an output signal, and a weight generation unit configured to monitor a variation of the output signal and generate weight information based on the monitored variation.Type: ApplicationFiled: April 1, 2011Publication date: June 21, 2012Inventors: Ji-Wang Lee, Shin-Deok Kang
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Publication number: 20120140870Abstract: An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.Type: ApplicationFiled: December 29, 2010Publication date: June 7, 2012Inventors: Ji-Wang LEE, Shin-Deok KANG
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Patent number: 8189400Abstract: A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.Type: GrantFiled: December 24, 2009Date of Patent: May 29, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hyung Soo Kim, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Jae Min Jang, Chang Kun Park
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Patent number: 8171189Abstract: A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to buffer data input through a data pad and output the buffered data. The synchronous data input buffer is configured to be synchronous with the internal clock to buffer the buffered data. The semiconductor apparatus is arranged so that the length of a line for transferring the internal clock to the synchronous data input buffer and the length of a line for transferring the buffered data to the synchronous data input buffer are substantially equal to each other.Type: GrantFiled: December 29, 2009Date of Patent: May 1, 2012Assignee: Hynix Semiconductor Inc.Inventors: Ji Wang Lee, Hee Woong Song, Tae Jin Hwang
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Patent number: 8149953Abstract: A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.Type: GrantFiled: July 22, 2008Date of Patent: April 3, 2012Assignee: Hynix Semiconductor, Inc.Inventors: Hyung-Soo Kim, Kun-Woo Park, Yong-Ju Kim, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee
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Patent number: 8143940Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.Type: GrantFiled: December 31, 2008Date of Patent: March 27, 2012Assignee: Hynic Semiconductor Inc.Inventors: Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park