Patents by Inventor Ji-Won Jung

Ji-Won Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7613103
    Abstract: A turbo TCM decoder for performing a soft decision without performing a sector phase quantization is disclosed. The turbo TCM decoder includes: a symbol transformer for converting a received signal to signal bits of QPSK mode by using an I-axis coordinate and a Q-axis coordinate on a constellation of the received signal; a phase sector quantizer for performing a phase sector quantization or the received signal by using the I-axis coordinate and the Q-axis coordinate; a first decoder for determining coded data by decoding the converted signal bits; a delay for delaying the quantized signal; and a second decoder for determining un-coded data by using the delayed quantized signal and the determined coded data.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: November 3, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun-A Choi, Nae-Soo Kim, Ji-Won Jung
  • Patent number: 7539920
    Abstract: Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: May 26, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun-A Choi, Nae-Soo Kim, Deock-Gil Oh, Ji-Won Jung
  • Publication number: 20080212130
    Abstract: An apparatus and method for compressing data. The apparatus can properly select any one of two compression codecs (i.e., the lossless codec and the lossy codec) according to compression capacities, compress the print data using the selected compression codec, and store the compressed data in the memory, such that an overall compression rate is decreased and the memory efficiency increases. Although the data is compressed by the lossy codec and a low compression rate is provided, the user may not notice the deterioration of the image quality. The method for compressing data includes compressing print data using a first codec; storing the compressed data in a memory; monitoring a compression capacity of the stored data; stopping the compression using the first codec based on the compression capacity, and re-compressing the print data using a second codec; and storing the re-compressed data in the memory.
    Type: Application
    Filed: February 7, 2008
    Publication date: September 4, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Ji Won JUNG
  • Patent number: 7340002
    Abstract: A pragmatic trellis code modulation decoder including a demodulator for receiving a modulated signal and computing coordination values of symbols of the modulated signal on an I-axis and Q-axis in a constellation; a coset mapper for generating 3-bit soft decision data based on the computed coordinate values; a viterbi decoder for receiving 3-bit soft decision data and generating 1-bit data as a coded data by decoding the 3-bit soft decision data; a re-encoder for receiving the 1-bit data from the viterbi decoder and obtaining un-coded information in order to compute an un-coded data; a sector phase quantizer for obtaining I channel and Q channel information based on the coordination values from the demodulator in order to obtain un-coded data; a time delayer for delaying output of the sector phase quantizer until the re-encoder outputs the un-coded information; and a non-coded code decoder for computing the un-coded data.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: March 4, 2008
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun A Choi, Nae-soo Kim, Deock Gil Oh, Ji Won Jung
  • Patent number: 7325174
    Abstract: The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (?) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: January 29, 2008
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun-A Choi, Nae-Soo Kim, Ji-Won Jung, Sung-Jun Cho, Tae-Gil Lee, Sang-Jin Park, In-Ki Lee
  • Publication number: 20060136799
    Abstract: Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.
    Type: Application
    Filed: November 2, 2005
    Publication date: June 22, 2006
    Inventors: Eun-A Choi, Nae-Soo Kim, Deock-Gil Oh, Ji-Won Jung
  • Publication number: 20050144543
    Abstract: The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (?) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.
    Type: Application
    Filed: July 9, 2004
    Publication date: June 30, 2005
    Inventors: Eun-A Choi, Nae-Soo Kim, Ji-Won Jung, Sung-Jun Cho, Tae-Gil Lee, Sang-Jin Park, In-Ki Lee
  • Publication number: 20050141409
    Abstract: A turbo TCM decoder for performing a soft decision without performing a sector phase quantization is disclosed. The turbo TCM decoder includes: a symbol transformer for converting a received signal to signal bits of QPSK mode by using an I-axis coordinate and a Q-axis coordinate on a constellation of the received signal; a phase sector quantizer for performing a phase sector quantization or the received signal by using the I-axis coordinate and the Q-axis coordinate; a first decoder for determining coded data by decoding the converted signal bits; a delay for delaying the quantized signal; and a second decoder for determining un-coded data by using the delayed quantized signal and the determined coded data.
    Type: Application
    Filed: September 3, 2004
    Publication date: June 30, 2005
    Inventors: Eun-A Choi, Nae-Soo Kim, Ji-Won Jung
  • Publication number: 20050112600
    Abstract: The present invention relates to screening of the expression profile of muscle specific genes according to the growing stages in swine and a functional cDNA chip using the same and provides expression files of the muscle specific genes specifically expressed according to the growing stages in the muscle and fat tissues of swine. Also, the present invention provides a functional cDNA chip for meat quality evaluation and screening of specific genes in swine prepared by integrating only the muscle specific genes screened as described above. Therefore, the functional cDNA chip can be used to evaluate of meat quality according to breeds of swine and to bring a high meat quality swine.
    Type: Application
    Filed: February 27, 2004
    Publication date: May 26, 2005
    Inventors: Chul-Wook Kim, Jung-Sou Yeo, Jung-Gyu Lee, Young-Min Song, Kwang-Keun Cho, Ki-Hwa Chung, Il-Suk Kim, Sang-Keun Jin, Su-Hyun Park, Ji-Won Jung, Min-Jung Lee, Eun-Jung Kwon, Eun-Segk Cho, Hwok-Rai Cho, Sun-Min Shin, Hee-Sun Nam, Yeon-Hee Hong, Sung-Kwang Hong, Yang-Su Kang, Young-Joo Ha, Jeong-Man Rou, Suk-Chun Kwack, In-Ho Choi, Byeong-Woo Kim
  • Publication number: 20050112599
    Abstract: The present invention relates to screening of the expression profile of fat specific genes according to the growing stages in swine and a functional cDNA chip using the same and provides expression files of the fat specific genes specifically expressed according to the growing stages in the muscle and fat tissues of swine. Also, the present invention provides a functional cDNA chip for meat quality evaluation and screening of specific genes in swine prepared by integrating only the fat specific genes screened as described above. Therefore, the functional cDNA chip can be used to evaluate of meat quality according to breeds of swine and to bring a high meat quality swine.
    Type: Application
    Filed: February 27, 2004
    Publication date: May 26, 2005
    Inventors: Chul-Wook Kim, Jung-Sou Yeo, Jung-Gyu Lee, Young-Min Song, Kwang-Keun Cho, Ki-Hwa Chung, Il-Suk Kim, Sang-Keun Jin, Su-Hyun Park, Ji-Won Jung, Min-Jung Lee, Eun-Jung Kwon, Eun-Segk Cho, Hwok-Rai Cho, Sun-Min Shin, Hee-Sun Nam, Yeon-Hee Hong, Sung-Kwang Hong, Yang-Su Kang, Young-Joo Ha, Jeong-Man Rou, Suk-Chun Kwack, In-Ho Choi, Byeong-Woo Kim
  • Publication number: 20050112602
    Abstract: The present invention relates to a cDNA chip for screening and function analysis of swine genes and provides a cDNA chip comprising a probe to detect marker genes specifically expressed in the muscle and fat tissues of swine, in which the probe is capable of complementarily bind to the marker genes. Also, the present invention provides expression profiles of marker genes which are related to economic traits of swine by using the cDNA chip according to the present invention. Therefore, the cDNA chip according to the present invention can be used for the comparison of genetic expression according to swine breeds and tissues, genetic mutation screening, genetic polymorphism interpretation, development of new drugs for disease treatment and disease diagnosis, swine improvement.
    Type: Application
    Filed: February 27, 2004
    Publication date: May 26, 2005
    Inventors: Chul-Wook Kim, Jung-Sou Yeo, Jung-Gyu Lee, Young-Min Song, Kwang-Keun Cho, Ki-Hwa Chung, Il-Suk Kim, Sang-Keun Jin, Su-Hyun Park, Ji-Won Jung, Min-Jung Lee, Eun-Jung Kwon, Eun-Segk Cho, Hwok-Rai Cho, Sun-Min Shin, Hee-Sun Nam, Yeon-Hee Hong, Sung-Kwang Hong, Yang-Su Kang, Young-Joo Ha, Jeong-Man Rou, Suk-Chun Kwack, In-Ho Choi, Byeong-Woo Kim
  • Publication number: 20040117720
    Abstract: A pragmatic trellis code modulation decoder is disclosed.
    Type: Application
    Filed: November 21, 2003
    Publication date: June 17, 2004
    Inventors: Eun A. Choi, Nae-Soo Kim, Deock Gil Oh, Ji Won Jung
  • Patent number: 5936922
    Abstract: In a method for exactly sampling a synchronous pattern from read data including an error from a recording medium and an apparatus for carrying out the method, a system clock signal is received and the starting portion of each data region concerning the read data from the recording medium having a track structure is counted by using the received system clock signal. The counting value is compared with a standard counting value and the present data region is judged according to the compared result. A same random synchronous signal as a synchronous pattern concerning the data region judged from each data region of the read data, is generated. A first and a second sampling signals are generated in a synchronization block of a unit based on the first and the second synchronous pattern generated from the random synchronous signal. A normal synchronous pattern concerning each data region is sampled based on the random synchronous signal and on the first and the second sampling signals.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: August 10, 1999
    Assignee: Daewoo Electronics Co., Ltd.
    Inventors: Ji-Won Jung, Seung-Hyun Nam