Abstract: An apparatus for measuring an adhesion force, the apparatus comprising a stage configured to support a specimen, and a sensor adhered to the specimen, wherein the sensor detects the adhesion force of the specimen, the adhesion force of the specimen being a force for detaching the sensor from the specimen.

Abstract: A case includes a base plate, a hole formed through the base plate, a pattern that is on one surface of the base plate and includes a plurality of crests and a plurality of troughs. The case further includes an inclined area that is between the hole and the pattern, and at least one step that is between the inclined area and the hole, in which a first angle that the inclined area forms with a central axis of the hole is greater than a second angle that is an angle of view through the hole.

Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

Abstract: Disclosed are a method for DNA extraction in a sample for next generation sequencing (NGS) and a method of constructing a NGS library using the extracted DNA. The method for DNA extraction includes: preparing a mixture by mixing a biological sample with a buffer; applying microwaves to the mixture; and recovering DNA. The method of constructing a NGS library includes: extracting DNA according to the method for DNA extraction; amplifying a target DNA using primers; and purifying the amplified product and subjecting the purified product to library pooling.

Abstract: A lower semiconductor package of a package-on-package type semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate; a chip connecting terminal disposed between the semiconductor chip and the package substrate and configured to connect the semiconductor chip to the package substrate; conductive pillars arranged on the package substrate to at least partially surround the semiconductor chip; and a dam structure configured to cover the conductive pillars on the package substrate and having a first opening at least partially surrounding the semiconductor chip.

Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

Abstract: Disclosed is a semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, a connection solder pattern between the package substrate and the semiconductor chip, and a dummy bump between the package substrate and the semiconductor chip and spaced apart from the connection solder pattern. The connection solder pattern includes a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer. The dummy bump includes a dummy pillar and a dummy solder pattern. A thickness of the dummy solder pattern is less than a thickness of the connection solder pattern. A melting point of the dummy solder pattern is greater than that of the connection solder layer.

Abstract: A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, the semiconductor chip including a first surface facing the lower substrate and a second surface opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip, the upper substrate including a lower surface on which support members protruding toward the second surface of the semiconductor chip are disposed; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant filling a space between the lower substrate and the upper substrate and encapsulating at least a portion of the semiconductor chip and the connection structure; and adhesive members disposed on the second surface of the semiconductor chip such as to correspond to the support members, respectively, the adhesive members disposed in contact with the second surface and the support members.

Abstract: A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.

Abstract: Provided is a mounting substrate for a semiconductor package, including a substrate having an upper surface and a lower surface opposite to each other, the substrate including a plurality of insulation layers and wirings in the plurality of insulation layers, first substrate pads and second substrate pads on the upper surface in a chip mounting region of the mounting surface, heat absorbing pads on the upper surface in a peripheral region of the mounting surface adjacent to the chip mounting region, and connection lines in the substrate, the connection lines being configured to thermally couple the heat absorbing pads and the second substrate pads to each other.

Abstract: A lower semiconductor package of a package-on-package type semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate; a chip connecting terminal disposed between the semiconductor chip and the package substrate and configured to connect the semiconductor chip to the package substrate; conductive pillars arranged on the package substrate to at least partially surround the semiconductor chip; and a dam structure configured to cover the conductive pillars on the package substrate and having a first opening at least partially surrounding the semiconductor chip.

Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

Abstract: Disclosed is a method of providing biological data. The method includes the following steps performed by a data processing device: selecting a biological data set from a biological data pool; encrypting biological data included in the biological data set to produce encrypted biological data; transferring the encrypted biological data to a user; receiving a result of analysis on the encrypted biological data from the user; and transferring information on the encrypted biological data included in the result of the analysis to the user. The data processing device encrypts the biological data with a key determined according to a combination of biological data constituting the biological data set.

Abstract: Disclosed are a method for DNA extraction in a sample for next generation sequencing (NGS) and a method of constructing a NGS library using the extracted DNA. The method for DNA extraction includes: preparing a mixture by mixing a biological sample with a buffer; applying microwaves to the mixture; and recovering DNA. The method of constructing a NGS library includes: extracting DNA according to the method for DNA extraction; amplifying a target DNA using primers; and purifying the amplified product and subjecting the purified product to library pooling.

Abstract: Disclosed is a molded article including a base layer, a surface layer having a resin and formed to cover at least a portion of the base layer, and a reflective material mixed with the resin and reflecting light, wherein the reflective material includes a metal flake, and a metal oxide layer stacked on the metal flake.

Abstract: A mobile office storage assembly includes a housing including a top wall, a lower-most bottom wall and a pair of sidewalls that cooperate to define an interior storage space, a first horizontal surface movable between a retracted position where a majority of the first horizontal surface is positioned below the bottom wall and an extended position where the first horizontal surface is positioned outwardly with respect to the retracted position, and a second horizontal surface movable between a retracted position where a majority of the second horizontal surface is positioned below the bottom wall and an extended position where the second horizontal surface is positioned outwardly with respect to the retracted position of the second horizontal work surface.

Abstract: A method for bonding a semiconductor package includes loading a semiconductor chip on a substrate, and bonding the semiconductor chip to the substrate by using a bonding tool, the bonding tool including a pressing surface for pressing the semiconductor chip, and an inclined surface extending from one side of the pressing surface. Bonding the semiconductor chip to the substrate includes deforming a bonding agent disposed between the substrate and the semiconductor chip by pressing the bonding tool, and deforming the bonding agent includes generating a fillet by protruding a portion of the bonding agent beyond the semiconductor chip, and growing the fillet in such a way that a top surface of the fillet is grown in an extending direction of the inclined surface.