Abstract: A mobile device includes a slave device that receives first data provided to a serial data line in synchronization with a clock signal provided through a serial clock line, and outputs second data to the serial data line in synchronization with the clock signal; and a master device that generates the clock signal and provides the first data to the serial data line in synchronization with the generated clock signal, or receives the second data output to the serial data line in synchronization with the clock signal. The master device generates the clock signal of a first frequency upon transmitting the first data, and generates the clock signal of a second frequency, which is lower than the first frequency, upon receiving the second data.

Abstract: A mobile device includes a slave device that receives first data provided to a serial data line in synchronization with a clock signal provided through a serial clock line, and outputs second data to the serial data line in synchronization with the clock signal; and a master device that generates the clock signal and provides the first data to the serial data line in synchronization with the generated clock signal, or receives the second data output to the serial data line in synchronization with the clock signal. The master device generates the clock signal of a first frequency upon transmitting the first data, and generates the clock signal of a second frequency, which is lower than the first frequency, upon receiving the second data.

Abstract: A page descriptor can be stored in advance in a memory management unit under various conditions so that an address translation overhead can be reduced. The memory management unit comprises an address translation unit that receives a memory access request as a virtual address and translates the virtual address to a physical address. A translation lookaside buffer (TLB) stores page descriptors of a plurality of physical addresses, the address translation unit determining whether a page descriptor corresponding to a received virtual address is present in the translation lookaside buffer. A prefetch buffer stores page descriptors of the plurality of physical addresses.

Abstract: A memory management unit comprises an address translation unit that receives a memory access request as a virtual address and translates the virtual address to a physical address. A translation lookaside buffer stores page descriptors of a plurality of physical addresses, the address translation unit determining whether a page descriptor of a received virtual address is present in the translation lookaside buffer. A prefetch buffer stores page descriptors of the plurality of physical addresses. The address translation unit, in the event the page descriptor of the received virtual address is not present in the translation lookaside buffer, further determines whether the page descriptor of the received virtual address is present in the prefetch buffer; updates the translation lookaside buffer with the page descriptor in response to the determination; and performs a translation of the virtual address to a physical address using the page descriptor.