Abstract: A semiconductor memory device includes a stack structure and a slit structure. The stack structure includes insulation layers and conductive layers alternately stacked with the insulation layers. The slit structure is configured to divide the stack structure into memory blocks. A part of the slit structure configured to define one memory block has a dashed shape including a slit region and a bridge region.

Abstract: A semiconductor memory device includes a stack structure and a slit structure. The stack structure includes insulation layers and conductive layers alternately stacked with the insulation layers. The slit structure is configured to divide the stack structure into memory blocks. A part of the slit structure configured to define one memory block has a dashed shape including a slit region and a bridge region.

Abstract: A semiconductor memory device includes a stack structure and a slit structure. The stack structure includes insulation layers and conductive layers alternately stacked with the insulation layers. The slit structure is configured to divide the stack structure into memory blocks. A part of the slit structure configured to define one memory block has a dashed shape including a slit region and a bridge region.

Abstract: Provided are a semiconductor device, a semiconductor package, and an electronic system. The device includes a substrate having a front side and a back side disposed opposite the front side. An internal circuit is disposed on or near to the front side of the substrate. Signal I/O through-via structures are disposed in the substrate. Back side conductive patterns are disposed on the back side of the substrate and electrically connected to the signal I/O through-via structures. A back side conductive structure is disposed on the back side of the substrate and spaced apart from the signal I/O through-via structures. The back side conductive structure includes parallel supporter portions.

Abstract: A vertical memory device includes a channel, a conductive pattern, gate electrodes, a bit line and a conductive line. A plurality of the channels and the conductive patterns extend in a vertical direction from a top surface of a substrate. The gate electrodes surround outer sidewalls of the channels and the conductive patterns. The gate electrodes are stacked in the vertical direction to be spaced apart from each other. The bit line is electrically connected to the channels. The conductive line is electrically connected to the conductive patterns.

Abstract: Provided are a semiconductor device, a semiconductor package, and an electronic system. The device includes a substrate having a front side and a back side disposed opposite the front side. An internal circuit is disposed on or near to the front side of the substrate. Signal I/O through-via structures are disposed in the substrate. Back side conductive patterns are disposed on the back side of the substrate and electrically connected to the signal I/O through-via structures. A back side conductive structure is disposed on the back side of the substrate and spaced apart from the signal I/O through-via structures. The back side conductive structure includes parallel supporter portions.

Abstract: An example embodiment relates to a semiconductor memory device including a plurality of cylindrical bottom electrodes arranged in a first direction and in a second direction. The device includes a supporting base configured to support the plurality of cylindrical bottom electrodes by contacting side surfaces of the plurality of cylindrical bottom electrodes. The supporting base includes first patterns in which first open areas are formed, and second patterns in which second open areas are formed. The first patterns and the second patterns have different oriented shapes.

Abstract: An example embodiment relates to a semiconductor memory device including a plurality of cylindrical bottom electrodes arranged in a first direction and in a second direction. The device includes a supporting base configured to support the plurality of cylindrical bottom electrodes by contacting side surfaces of the plurality of cylindrical bottom electrodes. The supporting base includes first patterns in which first open areas are formed, and second patterns in which second open areas are formed. The first patterns and the second patterns have different oriented shapes.

Abstract: A semiconductor device includes a substrate having a cell array region and a peripheral circuit region, a lower structure on the substrate in the cell array region, a first insulation layer on the substrate across the cell array region and the peripheral circuit region, the lower structure being covered with the first insulation layer, a capacitor on the first insulation layer in the cell array region, the capacitor including a lower electrode, a dielectric layer patter, and an upper electrode, a second insulation layer on the first insulation layer, the capacitor being covered with the second insulation layer, a first upper wiring structure on the second insulation layer, the first upper wiring structure being electrically connected to the capacitor and including an upper wiring and a mask pattern, and at least one dummy structure in the peripheral circuit region.