Abstract: The present disclosure relates to methods for obtaining channel state information (CSI), apparatus, and computer storage medium. One example method includes allocating, by a network device to a terminal device according to a preset rule, a transmission resource for transmitting a sounding reference signal (SRS) in a cell to which the terminal device belongs. Transmission resources for transmitting SRSs in different cells do not overlap at all or partially overlap. The network device receives the SRS transmitted by the terminal device on the allocated transmission resource, and performs channel quality estimation based on the received SRS to obtain CSI.

Abstract: A reshaping method for metal product includes acquiring position data information of a workpiece; converting the position data information into coordinate information, and fitting the coordinate information to obtain a surface contour curve of the workpiece; comparing the surface contour curve with a standard contour curve to generate a comparison result; obtaining reshaping information of the workpiece based on the comparison result; and controlling the reshaping system to reshape the workpiece. The disclosure acquires position data information of the workpiece by measuring, converts the position data information into coordinate information, fits the coordinate information to obtain the surface contour curve of the workpiece, compares the surface contour curve with the standard contour curve to obtain deformation situation, and reshapes the workpiece according to the reshaping information based on the deformation situation, which improves efficiency of workpiece reshaping and reducing labor costs.

Abstract: In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.

Abstract: In an example, a three-dimensional (3D) memory device includes a memory stack and a through stair contact (TSC). The memory stack includes interleaved conductive layers and dielectric layers. The memory stack includes stairs in a staircase region. The TSC extends through the memory stack in the staircase region. The TSC includes a first conductor layer and a first spacer circumscribing the first conductor layer. The first conductor layer of the TSC is insulated from the conductive layers of the memory stack by the first spacer.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. First, a slit structure and a support structure are formed in a stack structure having interleaved a plurality of sacrificial material layers and a plurality of insulating material layers, the initial support structure between adjacent slit openings of the slit structure. A source structure is formed to include a source portion in each of the slit openings. A pair of first portions of a connection layer is formed in contact with and conductively connected to the source portion. A second portion of the connection layer is formed in contact with and conductively to the pair of first portions of the connection layer.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a first source contact portion in a substrate, forming a dielectric stack over the first source contact portion, and forming a slit opening extending in the dielectric stack and exposing the first source contact portion. The method also includes forming a plurality of conductor layers through the slit opening and form a second source contact portion in the slit opening and in contact with the first source contact portion.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers, a plurality of channel structures extending in the memory stack, and a source structure extending in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. Two adjacent source contacts are conductively connected to one another by a connection layer, the connection layer includes a pair of first portions being over the two adjacent ones of the plurality of source contacts and a second portion between the pair of first portions. A support structure is between the two adjacent source contacts. The support structure includes a cut structure over interleaved a plurality of conductor portions and a plurality of insulating portions.

Abstract: Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer.

Abstract: In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.

Abstract: Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. A cut structure is first formed in a stack structure. The stack structure includes interleaved initial sacrificial layers and initial insulating layers. A patterned cap material layer is formed over the stack structure. The patterned cap material layer includes an opening over the cut structure. Portions of the stack structure and the patterned cap material layer adjacent to the opening are removed to form a slit structure and an initial support structure. The initial support structure divides the slit structure into slit openings. Conductor portions are formed through the plurality of slit openings to form a support structure. A source contact is formed in each slit opening. A connection layer is formed over the source contact in each slit opening and over the support structure.

Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs, a channel structure extending vertically through the conductor/dielectric layer pairs in the memory stack, a TAC extending vertically through the conductor/dielectric layer pairs in the memory stack, and a dummy channel structure filled with a dielectric layer and extending vertically through the conductor/dielectric layer pairs in the memory stack.

Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed.

Abstract: Embodiments of counter-stress structures and methods for forming the same are disclosed. The present disclosure describes a semiconductor wafer including a substrate having a dielectric layer formed thereon and a device region in the dielectric layer. The device region includes at least one semiconductor device. The semiconductor wafer further includes a sacrificial region adjacent to the device region, wherein the sacrificial region includes at least one counter-stress structure configured to counteract wafer stress formed in the device region.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack over a substrate, a plurality of channel structures, a source structure, and a support structure. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure includes a plurality of source portions and extending in the memory stack. The support structure is between adjacent ones of the source portions and has a plurality of interleaved conductor portions and insulating portions. A top one of the conductor portions is in contact with a top one of the conductor layers. Adjacent ones of the source portions are conductively connected to one another.

Abstract: A method includes: obtaining user equipment distribution information of a beam domain, where there are at least two beam domains, and the beam domain is a vertical area in a physically vertical dimension of a cell coverage area; determining information about a concentrated beam domain based on the user equipment distribution information, where the concentrated beam domain is a beam domain in which a quantity of covered user equipments exceeds a quantity threshold; and compared with information about a historical concentrated beam domain, if the information about the concentrated beam domain satisfies a preset condition, adjusting a broadcast beam domain based on the information about the concentrated beam domain, so that a main lobe direction of the broadcast beam domain is adjusted to a beam domain corresponding to the concentrated beam domain.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a substrate, a memory stack on the substrate; and a source contact structure extending vertically through the memory stack. The source contact structure includes a first source contact portion in the substrate and having a conductive material different from the substrate. The source contact structure also includes a second source contact portion above, in contact with, and conductively connected to the first source contact portion.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. First, a slit structure and a support structure are formed in a stack structure having interleaved a plurality of sacrificial material layers and a plurality of insulating material layers, the initial support structure between adjacent slit openings of the slit structure. A source structure is formed to include a source portion in each of the slit openings. A pair of first portions of a connection layer is formed in contact with and conductively connected to the source portion. A second portion of the connection layer is formed in contact with and conductively to the pair of first portions of the connection layer.