Patents by Inventor Ji-yeon Yang

Ji-yeon Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120062280
    Abstract: An output driver includes a control signal generation unit configured to generate a control signal in response to a driving strength signal and a power supply voltage level, and a driving signal generation unit configured to buffer a pre-driving signal and generate a driving signal for driving an output data, wherein a driving strength of the driving signal is adjusted in response to the control signal.
    Type: Application
    Filed: February 24, 2011
    Publication date: March 15, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventors: Ji Yeon YANG, Dong Uk LEE
  • Publication number: 20110058432
    Abstract: A semiconductor integrated circuit is provided that includes a first pad, a data storage and input/output block configured to store and output data by using a data strobe signal and a clock signal inputted through the first pad, and a timing compensation unit configured to delay the clock signal to generate the data strobe signal.
    Type: Application
    Filed: December 29, 2009
    Publication date: March 10, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Ji Yeon YANG, Kwan Weon KIM
  • Patent number: 7821292
    Abstract: An impedance calibration period setting circuit includes a command decoder and an impedance calibration activation signal generator. The command decoder combines external signals to generate a refresh signal. The impedance calibration activation signal generator is configured to generate an impedance calibration activation signal in response to the refresh signal and an address signal. The impedance calibration period setting circuit prevents abnormal changes in an impedance calibration code and reduces current consumption.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: October 26, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ji Yeon Yang, Dong Uk Lee
  • Publication number: 20100156455
    Abstract: An impedance calibration period setting circuit includes a command decoder and an impedance calibration activation signal generator. The command decoder combines external signals to generate a refresh signal. The impedance calibration activation signal generator is configured to generate an impedance calibration activation signal in response to the refresh signal and an address signal. The impedance calibration period setting circuit prevents abnormal changes in an impedance calibration code and reduces current consumption.
    Type: Application
    Filed: June 29, 2009
    Publication date: June 24, 2010
    Inventors: Ji Yeon YANG, Dong Uk LEE
  • Publication number: 20100142297
    Abstract: A data driver is presented in which the data driver includes a termination/pull-up driver and a pull-down driver. The termination/pull-up driver is configured to perform a termination operation and a pull-up operation at the same time for a data output terminal during an active interval of a semiconductor memory. The pull-down driver is configured to be activated when the semiconductor memory performs a read operation, and configured to pull down the output terminal in response to a level of an input data.
    Type: Application
    Filed: June 30, 2009
    Publication date: June 10, 2010
    Inventors: Dong Uk LEE, Ji Yeon YANG
  • Patent number: 7521246
    Abstract: Provided is a cell lysis method including: preparing a cell sample to be lysed; heating the cell sample; and cooling the cell sample by causing an endothermic reaction near the cell sample. According to the method, cell lysis can be simply and conveniently performed without regard to location and without additional devices since a separate energy source is not required and the apparatus is portable. In particular, when cell lysis is performed in a biochip using a small amount of sample, a greater cell lysis effect can be obtained. In addition, cell lysis efficiency is significantly improved, compared to when only heating is performed.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-yeon Yang, Yoon-kyoung Cho, Jin-tae Kim, Sook-young Kim, Young-sun Lee
  • Publication number: 20060258012
    Abstract: Provided is a cell lysis method including: preparing a cell sample to be lysed; heating the cell sample; and cooling the cell sample by causing an endothermic reaction near the cell sample. According to the method, cell lysis can be simply and conveniently performed without regard to location and without additional devices since a separate energy source is not required and the apparatus is portable. In particular, when cell lysis is performed in a biochip using a small amount of sample, a greater cell lysis effect can be obtained. In addition, cell lysis efficiency is significantly improved, compared to when only heating is performed.
    Type: Application
    Filed: January 19, 2006
    Publication date: November 16, 2006
    Inventors: Ji-yeon Yang, Yoon-kyoung Cho, Jin-tae Kim, Sook-young Kim, Young-sun Lee