Patents by Inventor Ji-Yeong HWANG
Ji-Yeong HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957476Abstract: Disclosed is a method of identifying dementia by at least one processor of a device. The method includes performing a first task that causes a first object to be displayed on a first region of a screen displayed on a user terminal; and when a preset condition is satisfied, performing a second task that causes at least one object, which induces the user's gaze, to be displayed instead of the first object on the screen of the user terminal.Type: GrantFiled: November 23, 2022Date of Patent: April 16, 2024Assignee: HAII CO, LTD.Inventors: Ho Yung Kim, Bo Hee Kim, Dong Han Kim, Hye Bin Hwang, Chan Yeong Park, Ji An Choi
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Publication number: 20240081722Abstract: A method of identifying dementia is disclosed that includes causing a user terminal to display an N-th screen including a plurality of objects. The user terminal may further display an N+1-th screen with the objects rearranged at positions on the N+1-th screen which are different from positions of the objects included in the N-th screen when an N-th selection input of selecting any one from among the objects included in the N-th screen is received. When an N+1-th selection input for selecting any one from among the objects included in the N+1-th screen is received, a third task of determining whether an answer of the N+1-th selection input is correct is performed based on whether the object selected from the N+1-th selection input is the same as at least one object selected from at least one previous selection input including the N-th selection input.Type: ApplicationFiled: July 7, 2022Publication date: March 14, 2024Applicant: HAII corp.Inventors: Ho Yung KIM, Geon Ha KIM, Bo Hee KIM, Dong Han KIM, Hye Bin HWANG, Chan Yeong PARK, Ji An CHOI, Bo Ri KIM
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Patent number: 11152390Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: June 16, 2020Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Publication number: 20200312878Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-il CHANG, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Patent number: 10700092Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: June 14, 2019Date of Patent: June 30, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Publication number: 20190296047Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: ApplicationFiled: June 14, 2019Publication date: September 26, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-il CHANG, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG
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Patent number: 10367002Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: October 7, 2016Date of Patent: July 30, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Publication number: 20170103998Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: ApplicationFiled: October 7, 2016Publication date: April 13, 2017Inventors: Sung-il Chang, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG