Patents by Inventor Ji Yeong YOON

Ji Yeong YOON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145719
    Abstract: A binder solution for an all-solid-state battery, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same, and more particularly to a binder solution for an all-solid-state battery, in which a polymer binder configured such that a non-polar functional group is bonded to the end of a polar functional group is used, whereby the polar functional group is provided by a deprotection mechanism of the polymer binder through a thermal treatment, thus increasing adhesion between electrode materials to thereby improve battery capacity and enabling a wet process to thereby reduce manufacturing costs, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Applicants: HYUNDAI MOTOR COMPANY, Kia Corporation, Seoul National University R&DB Foundation
    Inventors: Sang Mo Kim, Sang Heon Lee, Yong Sub Yoon, Jae Min Lim, Ju Yeong Seong, Jin Soo Kim, Jang Wook Choi, Kyu Lin Lee, Ji Eun Lee
  • Patent number: 11322475
    Abstract: A semiconductor package includes a package substrate having a hole pattern including a first through hole extending in a first direction and a second through hole extending in a second direction substantially perpendicular to the first direction, at least one first semiconductor chip disposed on the package substrate to overlap with the first through hole, at least one second semiconductor chip disposed on the package substrate to overlap with the second through hole, first bonding wires passing through the first through hole to electrically connect the at least one first semiconductor chip to the package substrate, and second bonding wires passing through the second through hole to electrically connect the at least one second semiconductor chip to the package substrate.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Hoon Lee, Ji Yeong Yoon
  • Patent number: 10998281
    Abstract: A package substrate of a semiconductor package includes second and third pad bonding portions respectively located at both sides of a first pad bonding portion disposed on a substrate body. First to third via landing portions are disposed to be spaced apart from the first to third pad bonding portions. First and second connection trace portions are disposed to be parallel with each other, and a first guard trace portion is disposed to be substantially parallel with the first connection trace portion. The second connection trace portion is connected to the first guard trace portion through a first connection plane portion, and the first connection plane portion connects the second connection trace portion to the second via landing portion. The third pad bonding portion is connected to the third via landing portion through a second connection plane portion.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Jae Hoon Lee, Sun Kyu Kong, Ji Yeong Yoon
  • Publication number: 20200286856
    Abstract: A semiconductor package includes a package substrate having a hole pattern including a first through hole extending in a first direction and a second through hole extending in a second direction substantially perpendicular to the first direction, at least one first semiconductor chip disposed on the package substrate to overlap with the first through hole, at least one second semiconductor chip disposed on the package substrate to overlap with the second through hole, first bonding wires passing through the first through hole to electrically connect the at least one first semiconductor chip to the package substrate, and second bonding wires passing through the second through hole to electrically connect the at least one second semiconductor chip to the package substrate.
    Type: Application
    Filed: October 2, 2019
    Publication date: September 10, 2020
    Applicant: SK hynix Inc.
    Inventors: Jae Hoon LEE, Ji Yeong YOON
  • Publication number: 20200176406
    Abstract: A package substrate of a semiconductor package includes second and third pad bonding portions respectively located at both sides of a first pad bonding portion disposed on a substrate body. First to third via landing portions are disposed to be spaced apart from the first to third pad bonding portions. First and second connection trace portions are disposed to be parallel with each other, and a first guard trace portion is disposed to be substantially parallel with the first connection trace portion. The second connection trace portion is connected to the first guard trace portion through a first connection plane portion, and the first connection plane portion connects the second connection trace portion to the second via landing portion. The third pad bonding portion is connected to the third via landing portion through a second connection plane portion.
    Type: Application
    Filed: August 13, 2019
    Publication date: June 4, 2020
    Applicant: SK hynix Inc.
    Inventors: Jae Hoon LEE, Sun Kyu KONG, Ji Yeong YOON