Patents by Inventor Ji YIN

Ji YIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105814
    Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: Che-Lun Chang, Jiun-Ming Kuo, Ji-Yin Tsai, Yuan-Ching Peng
  • Publication number: 20240045561
    Abstract: An area of a graphical user interface that potentially comprises an actionable graphical object is identified. An actional graphical object is an object that generates an event when clicked on. For example, an actional graphical object may be a button, a menu, a menu item, a check box, a text field, a text area, a tab, and/or the like. A cursor movement is generated in the area of the graphical user interface (e.g., using a grid). The cursor movement uses a scanning process to a detect a change in a cursor type (e.g., from an arrow cursor to a link cursor). In response to detecting the change in the cursor type, the actionable graphical object is identified in the area of the graphical interface. The actionable graphical object may then be integrated into a testing process to validate the graphical user interface.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: MICRO FOCUS LLC
    Inventors: GAOYANG ZHOU, PENG-JI YIN, CHENGZHE XU
  • Patent number: 11862709
    Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Lun Chang, Jiun-Ming Kuo, Ji-Yin Tsai, Yuan-Ching Peng
  • Publication number: 20230409167
    Abstract: Systems and methods include determining a target date; detecting a calendar in a graphical user interface; recognizing a month name in the detected calendar; recognizing one or more date numbers in the detected calendar; identifying a week start day for the detected calendar; identifying a position in the detected calendar associated with the target date based on the identified week start day for the detected calendar and the recognized one or more date numbers in the detected calendar; and automatically selecting the position in the detected calendar associated with the target date.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: MICRO FOCUS LLC
    Inventors: Peng-Ji YIN, Gaoyang Zhou, YunSheng LIU
  • Patent number: 11761360
    Abstract: A control method for a continuously variable valve lift mechanism includes: controlling a continuously variable valve lift mechanism to enter a limp mode when the continuously variable valve lift mechanism fails and disables an automatic valve lift changing function; driving and forcing the continuously variable valve lift mechanism to move to a maximum lift position; and triggering a self locking function to self lock the continuously variable valve lift mechanism at the maximum lift position when the continuously variable valve lift mechanism reaches the maximum lift position. A control system for a continuously variable valve lift mechanism, and a vehicle are also provided.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 19, 2023
    Assignee: GREAT WALL MOTOR COMPANY LIMITED
    Inventors: Tao Liu, Fabao Yang, Liming Xu, Ji Yin, Jiajia Hu, Luping Liu, Song Zhang, Yanlong Fang
  • Patent number: 11698851
    Abstract: A technique includes receiving, by a computer, user input representing creation of a first programmatic description of a first test object of source code to be tested. The technique includes, in response to receiving the user input, determining, by the computer, based on other programmatic descriptions of other test objects, a recommendation of a parameter to be used in the first programmatic description to identify the first test object. The technique includes causing, by the computer, a display of the recommendation.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: July 11, 2023
    Assignee: Micro Focus LLC
    Inventors: Peng-Ji Yin, Cheng Hua, Jie Zhang
  • Patent number: 11698849
    Abstract: Applications under test (AUT) may be tested by automated testing systems utilizing machine vision to recognize visual elements presented by the AUT and apply inputs to graphical elements, just as a human would. By utilizing the smallest image patch available, processing demands of the testing system are minimized. However, the image patch used to identify a portion of an AUT must be identifiable to the automated system. By selecting image patches that comprise the smallest size, but can be identified in an AUT by an automated system using machine vision, even as the AUT display is resized, reproportioned, noisy, or otherwise altered from the testing platform that was utilized for training.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: July 11, 2023
    Assignee: Micro Focus LLC
    Inventors: Peng-Ji Yin, Xiao-Fei Yu, Shuhui Fu, Yi-Bin Guo
  • Publication number: 20230197820
    Abstract: The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T1; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness t1 on the substrate at a second temperature T2; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature T3 less than T2, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor
    Type: Application
    Filed: June 7, 2022
    Publication date: June 22, 2023
    Inventors: Min Jiao, Ji-Yin Tsai, Da-Wen Lin, Hung-Ju Chou
  • Patent number: 11616133
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20230075004
    Abstract: An image of a graphical user interface is captured. A process is started to record identification of a graphical object (e.g., a text field) in the image of the graphical user interface. Recording identification of the graphical object in the image of the graphical user interface is based on machine learning. An end to the process to record identification of the graphical object in the image of the graphical user interface is identified. A machine learned software object is updated. For example, the machine learned software object is updated with a location of the graphical object. The updated machine learned software object then is used to test the graphical object. For example, to automatically fill in the text field using a test script.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 9, 2023
    Applicant: MICRO FOCUS LLC
    Inventors: Yun-Sheng Liu, Peng-Ji Yin, Er-Xin Shang, Gil Nakache, Tsachi Ben Zur, Anton Kaminsky, Shuhui Fu, Amos Nesher, Eyal Luzon
  • Publication number: 20220367690
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
  • Publication number: 20220352349
    Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Inventors: Che-Lun Chang, Jiun-Ming Kuo, Ji-Yin Tsai, Yuan-Ching Peng
  • Publication number: 20220336640
    Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 20, 2022
    Inventors: Meng-Ku Chen, Ji-Yin Tsai, Jeng-Wei Yu, Yi-Fang Pai, Pei-Ren Jeng, Yee-Chia Yeo, Chii-Horng Li
  • Publication number: 20220300396
    Abstract: An apparatus may include a processor (102) that may generate automated test scripts to test graphical user interface (GUI) functions of an application under test (AUT) (235). The apparatus may generate a screen element (220) that is overlaid onto at least one or all of the GUIs (210). The screen element (220) may therefore receive user inputs directed at the GUI (210), but block such inputs from being provided to the GUI (210). The user inputs received at the screen element (220) may be recorded in an automated test script for later replay. Blocking the user input may prevent a change in appearance of a GUI element (212) that would otherwise result from the user input, facilitating automated location of the GUI element (212) during replay of the automated test script.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 22, 2022
    Inventors: HUA-MING ZHAI, ER-XIN SHANG, PING-JI YIN
  • Patent number: 11448105
    Abstract: A valve mechanism includes a valve, a camshaft, an intermediate swing arm located between a cam and the valve, a lift regulating mechanism and a roller assembly. The cam drives the valve to move by means of the intermediate swing arm. The roller assembly is supported by the cam, an eccentric wheel of the lift regulating mechanism and an intermediate swing arm roller. A peripheral surface of the eccentric wheel includes a lift regulating section having a start point and an end point, a maximum lift point of the lift regulating section is located between the start point and the end point, and the lift regulating section is divided into a first section which is convex and a second section having at least a part thereof concave.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 20, 2022
    Assignee: GREAT WALL MOTOR COMPANY LIMITED
    Inventors: Tao Liu, Ji Yin, Luping Liu, Liming Xu, Jiajia Hu, Fabao Yang, Song Zhang, Yanlong Fang, Lei Wang
  • Publication number: 20220292011
    Abstract: Applications under test (AUT) may be tested by automated testing systems utilizing machine vision to recognize visual elements presented by the AUT and apply inputs to graphical elements, just as a human would. By utilizing the smallest image patch available, processing demands of the testing system are minimized. However, the image patch used to identify a portion of an AUT must be identifiable to the automated system. By selecting image patches that comprise the smallest size, but can be identified in an AUT by an automated system using machine vision, even as the AUT display is resized, reproportioned, noisy, or otherwise altered from the testing platform that was utilized for training.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 15, 2022
    Inventors: Peng-Ji Yin, Xiao-Fei Yu, Shuhui Fu, Yi-Bin Guo
  • Patent number: 11437497
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
  • Publication number: 20220262926
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 18, 2022
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Patent number: 11316030
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20220107883
    Abstract: A computing device includes a processor and a medium storing instructions. The instructions are executable by the processor to: identify, based on a blob detection analysis, a plurality of potential input elements in a graphical user interface (GUI); determine a set of rows including potential input elements that are in a horizontal alignment and in a same size range; determine a set of columns including potential input elements that are in a vertical alignment and in a same size range; determine a set of input elements comprising multiple potential input elements that are located at intersections of the identified set of rows and the identified set of columns; and perform automated testing of the GUI using the determined set of input elements.
    Type: Application
    Filed: December 28, 2018
    Publication date: April 7, 2022
    Applicant: MICRO FOCUS LLC
    Inventors: Peng-Ji YIN, Cheng HUA, Jie ZHANG