Abstract: A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data generated by the second processor; and a memory interface circuit configured to interface between the common memory and the first and second processors, the first processor being configured to demodulate and decode a signal received through wireless communication, and store the decoded data in the common memory via the memory interface circuit, the memory interface circuit being configured to read and decipher the decoded data stored in the common memory, and store the deciphered data in the common memory.

Abstract: Provided are a method of preparing an antibody with a regulated, sugar chain content, the method including the step of culturing antibody-expressing cells in a medium including glycerol as an additive for regulating the antibody sugar chain content, a method of preparing a high-quality population of antibodies by regulating the sugar content of the antibody to a desired content, and a population of antibodies prepared by the method. Further, provided is a method of regulating the antibody sugar chain content, the method including the step of culturing antibody-expressing cells in a medium including glycerol as an additive for regulating the antibody sugar chain content. Furthermore, provided is a medium composition, for regulating the antibody sugar chain content, the medium composition including glycerol as an additive for regulating the antibody sugar chain content.

Abstract: A processor includes; a processor core, a register selectively controlled by either external hardware during a first operation mode or the processor core during a second operation mode, and a selection circuit receiving first data provided by the external hardware to the register during the first operation mode and second data provided by the processor core to the register during the second operation mode.

Abstract: A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data generated by the second processor; and a memory interface circuit configured to interface between the common memory and the first and second processors, the first processor being configured to demodulate and decode a signal received through wireless communication, and store the decoded data in the common memory via the memory interface circuit, the memory interface circuit being configured to read and decipher the decoded data stored in the common memory, and store the deciphered data in the common memory.

Abstract: A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data generated by the second processor; and a memory interface circuit configured to interface between the common memory and the first and second processors, the first processor being configured to demodulate and decode a signal received through wireless communication, and store the decoded data in the common memory via the memory interface circuit, the memory interface circuit being configured to read and decipher the decoded data stored in the common memory, and store the deciphered data in the common memory.

Abstract: A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data generated by the second processor; and a memory interface circuit configured to interface between the common memory and the first and second processors, the first processor being configured to demodulate and decode a signal received through wireless communication, and store the decoded data in the common memory via the memory interface circuit, the memory interface circuit being configured to read and decipher the decoded data stored in the common memory, and store the deciphered data in the common memory.

Abstract: A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data generated by the second processor; and a memory interface circuit configured to interface between the common memory and the first and second processors, the first processor being configured to demodulate and decode a signal received through wireless communication, and store the decoded data in the common memory via the memory interface circuit, the memory interface circuit being configured to read and decipher the decoded data stored in the common memory, and store the deciphered data in the common memory.

Abstract: A processor includes; a processor core, a register selectively controlled by either external hardware during a first operation mode or the processor core during a second operation mode, and a selection circuit receiving first data provided by the external hardware to the register during the first operation mode and second data provided by the processor core to the register during the second operation mode.

Abstract: The present invention relates to a method for preparing a population of antibodies to have high purity and high quality by removing antibody isoforms and impurities through the use of a cation exchange column, a hydrophobic interaction column, and an anion exchange column successively, without using a protein A column; and to a population of antibodies prepared by the above method.

Abstract: A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data generated by the second processor; and a memory interface circuit configured to interface between the common memory and the first and second processors, the first processor being configured to demodulate and decode a signal received through wireless communication, and store the decoded data in the common memory via the memory interface circuit, the memory interface circuit being configured to read and decipher the decoded data stored in the common memory, and store the deciphered data in the common memory.

Abstract: Provided are a method of preparing an antibody with a regulated, sugar chain content, the method including the step of culturing antibody-expressing cells in a medium including glycerol as an additive for regulating the antibody sugar chain content, a method of preparing a high-quality population of antibodies by regulating the sugar content of the antibody to a desired content, and a population of antibodies prepared by the method. Further, provided is a method of regulating the antibody sugar chain content, the method including the step of culturing antibody-expressing cells in a medium including glycerol as an additive for regulating the antibody sugar chain content. Furthermore, provided is a medium composition, for regulating the antibody sugar chain content, the medium composition including glycerol as an additive for regulating the antibody sugar chain content.

Abstract: An apparatus and a method for scaling a dynamic bus clock are provided. The apparatus for scaling the dynamic bus clock includes at least one master module, at least one slave module, a bus for delivering data transmitted and received by the at least one master module and the at least one slave module, a bus frequency controller for determining a bus clock frequency by considering activity information of the at least one master module, and a clock generator for generating the frequency as determined by the bus frequency controller and providing the generated frequency to the at least one master module, the at least one slave module, and the bus.

Abstract: An apparatus and method for adaptively changing clock frequencies of a Central Processing Unit (CPU) and a bus in a digital system are provided. The system includes an Adaptive Frequency Scaling (AFS) controller and a clock controller. The AFS controller determines whether to change a clock frequency of the CPU according to operation information of the CPU, and determines whether to change a clock frequency of the bus according to operation information of the bus. The clock controller generates a clock frequency of the CPU and a clock frequency of the bus according to the determination of the AFS controller.

Abstract: The present invention relates to a method for preparing a population of antibodies to have high purity and high quality by removing antibody isoforms and impurities through the use of a cation exchange column, a hydrophobic interaction column, and an anion exchange column successively, without using a protein A column; and to a population of antibodies prepared by the above method.

Abstract: The present invention relates to a human monoclonal antibody that specifically binds to VCAM-1, and a therapeutic composition for the treatment of inflammatory disease or cancer comprising the same. The human monoclonal antibody according to the present invention shows a strong affinity to VCAM-1 expressed on human or mouse endothelial cell, effectively inhibits leukocyte adhesion to activated endothelial cells expressing VCAM-1, and shows a low immunogenicity, thereby being used for the treatment of cancer or inflammatory disease such as asthma, rhinitis, arthritis, multiple sclerosis, bowel disease, arteriosclerosis, myocardial infarction and transplant rejection.

Abstract: The present invention relates to a human recombinant monoclonal antibody that specifically binds to human Vascular Cell Adhesion Molecule-1 (VCAM-1) to inhibit adhesion between leukocytes and activated endothelial cells and transmigration of leukocytes through the activated endothelial cells, and a prophylactic and therapeutic composition for inflammatory disease or cancer comprising the same. The human recombinant monoclonal antibody according to the present invention shows a strong affinity to VCAM-1 expressed on human endothelial cell, and effectively inhibits VCAM-1-mediated adhesion between leukocytes and activated endothelial cells and transmigration of leukocytes through the activated endothelial cells, thereby being used for the prevention and treatment of inflammatory disease such as asthma and arthritis, transplant rejection, cardiovascular disease, and cancer.

Abstract: The present invention relates to a human monoclonal antibody that specifically binds to VCAM-1, and a therapeutic composition for the treatment of inflammatory disease or cancer comprising the same. The human monoclonal antibody according to the present invention shows a strong affinity to VCAM-1 expressed on human or mouse endothelial cell, effectively inhibits leukocyte adhesion to activated endothelial cells expressing VCAM-1, and shows a low immunogenicity, thereby being used for the treatment of cancer or inflammatory disease such as asthma, rhinitis, arthritis, multiple sclerosis, bowel disease, arteriosclerosis, myocardial infarction and transplant rejection.

Abstract: The present invention relates to a human recombinant monoclonal antibody that specifically binds to human Vascular Cell Adhesion Molecule-1 (VCAM-1) to inhibit adhesion between leukocytes and activated endothelial cells and transmigration of leukocytes through the activated endothelial cells, and a prophylactic and therapeutic composition for inflammatory disease or cancer comprising the same. The human recombinant monoclonal antibody according to the present invention shows a strong affinity to VCAM-1 expressed on human endothelial cell, and effectively inhibits VCAM-1-mediated adhesion between leukocytes and activated endothelial cells and transmigration of leukocytes through the activated endothelial cells, thereby being used for the prevention and treatment of inflammatory disease such as asthma and arthritis, transplant rejection, cardiovascular disease, and cancer.

Abstract: An apparatus and method for adaptively changing clock frequencies of a Central Processing Unit (CPU) and a bus in a digital system are provided. The system includes an Adaptive Frequency Scaling (AFS) controller and a clock controller. The AFS controller determines whether to change a clock frequency of the CPU according to operation information of the CPU, and determines whether to change a clock frequency of the bus according to operation information of the bus. The clock controller generates a clock frequency of the CPU and a clock frequency of the bus according to the determination of the AFS controller.

Abstract: An apparatus and a method for scaling a dynamic bus clock are provided. The apparatus for scaling the dynamic bus clock includes at least one master module, at least one slave module, a bus for delivering data transmitted and received by the at least one master module and the at least one slave module, a bus frequency controller for determining a bus clock frequency by considering activity information of the at least one master module, and a clock generator for generating the frequency as determined by the bus frequency controller and providing the generated frequency to the at least one master module, the at least one slave module, and the bus.