Abstract: A method for driving in a blind spot of a sensor mounted on an autonomous vehicle is provided. The method includes steps of: a computing device of the autonomous vehicle running on a specific road locating the autonomous vehicle from precision map information, sensor information and GPS information, and in response to determining that the autonomous vehicle is expected to encounter a specific event, transmitting vehicle location data, travelling direction data, vehicle structure data and sensor location data and sensor's viewing angle data to the server, to determine whether a region of interest corresponding to the specific event is included in blind spot candidates; receiving blind spot stereoscopic data, computed from the data received from the autonomous vehicle and 3D occlusion environmental data corresponding to occluding static objects in the blind spot candidates, from the server; and controlling movement of the autonomous vehicle based on the blind spot stereoscopic data.

Abstract: Provided is a substrate having an alignment mark, methods of aligning wafers and fabricating semiconductors. An alignment method of a wafer comprises providing a wafer on a wafer stage of a photolithography apparatus, irradiating light to the alignment mark, collecting reflected light from the alignment mark, analyzing optical information of the collected light, and determining a location of the wafer based on the analyzed optical information, wherein the wafer comprises a first surface having an alignment mark, the alignment mark including a first plurality of alignment patterns in a first row, and a second plurality of alignment patterns in a second row, the second plurality of alignment patterns being adjacent to the first plurality of alignment patterns, wherein the first plurality of alignment patterns are arranged in a row direction at a first pitch, and the second plurality of alignment patterns are arranged in the row direction at a second pitch different from the first pitch.

Abstract: Provided is a substrate having an alignment mark, methods of aligning wafers and fabricating semiconductors. An alignment method of a wafer comprises providing a wafer on a wafer stage of a photolithography apparatus, irradiating light to the alignment mark, collecting reflected light from the alignment mark, analyzing optical information of the collected light, and determining a location of the wafer based on the analyzed optical information, wherein the wafer comprises a first surface having an alignment mark, the alignment mark including a first plurality of alignment patterns in a first row, and a second plurality of alignment patterns in a second row, the second plurality of alignment patterns being adjacent to the first plurality of alignment patterns, wherein the first plurality of alignment patterns are arranged in a row direction at a first pitch, and the second plurality of alignment patterns are arranged in the row direction at a second pitch different from the first pitch.

Abstract: An overlay mark may include a main overlay pattern and an auxiliary overlay pattern, wherein the main overlay pattern may have an opening exposing a substrate and the auxiliary overlay pattern may be formed in the opening. The auxiliary overlay pattern may be spaced apart from a sidewall of the main overlay pattern defining the opening. The thickness ratio of the auxiliary overlay pattern to the main overlay pattern may be about 0.05:1 to about 0.30:1. Accordingly, overlay accuracy measurements may be improved using the clearer overlay mark according to example embodiments.

Abstract: Provided are a photomask and a method of fabricating a semiconductor device. The photomask includes a photomask substrate including a chip region and a scribe lane region, with an overlay mark formed in the scribe lane region. The overlay mark includes one or more sub-overlay marks. Each of the sub-overlay marks includes a plurality of unit regions sequentially connected to each other and having different widths, where the width of a given unit region is constant.

Abstract: The alignment marks formed in a scribe line of a semiconductor substrate include at least one main mark, a first sub-mark and second sub-marks. The first sub-mark is formed at a central portion of the main mark. The second sub-marks are disposed symmetrically with respect to the first sub-mark and are used for detecting asymmetry of the main mark by measuring distances between respective side edges of the main mark and the first sub-mark, and by measuring respective side edges between the main mark and each of the second sub-marks. Alternatively, the alignment marks include main outer and inner marks and a sub-mark disposed in between the main outer and inner marks. In this case, the sub-mark is used for detecting asymmetry of the main mark by measuring distances between respective side edges of the main outer mark and the sub-mark, and by measuring respective side edges between the main inner mark and the sub-mark.

Abstract: An overlay mark may include a main overlay pattern and an auxiliary overlay pattern, wherein the main overlay pattern may have an opening exposing a substrate and the auxiliary overlay pattern may be formed in the opening. The auxiliary overlay pattern may be spaced apart from a sidewall of the main overlay pattern defining the opening. The thickness ratio of the auxiliary overlay pattern to the main overlay pattern may be about 0.05:1 to about 0.30:1. Accordingly, overlay accuracy measurements may be improved using the clearer overlay mark according to example embodiments.

Abstract: Provided are a photomask and a method of fabricating a semiconductor device. The photomask includes a photomask substrate including a chip region and a scribe lane region, with an overlay mark formed in the scribe lane region. The overlay mark includes one or more sub-overlay marks. Each of the sub-overlay marks includes a plurality of unit regions sequentially connected to each other and having different widths, where the width of a given unit region is constant.

Abstract: The alignment marks formed in a scribe line of a semiconductor substrate include at least one main mark, a first sub-mark and second sub-marks. The first sub-mark is formed at a central portion of the main mark. The second sub-marks are disposed symmetrically with respect to the first sub-mark and are used for detecting asymmetry of the main mark by measuring distances between respective side edges of the main mark and the first sub-mark, and by measuring respective side edges between the main mark and each of the second sub-marks. Alternatively, the alignment marks include main outer and inner marks and a sub-mark disposed in between the main outer and inner marks. In this case, the sub-mark is used for detecting asymmetry of the main mark by measuring distances between respective side edges of the main outer mark and the sub-mark, and by measuring respective side edges between the main inner mark and the sub-mark.

Abstract: An overlay key formed in a scribe lane and used to align a circuit pattern may include a lower overlay mark formed on a metal silicide layer directly in contact with a silicon substrate. A method of forming an overlay key in a scribe lane may include providing a silicon substrate, forming a metal silicide layer to be in direct contact with the silicon substrate, and forming a lower overlay mark on the metal silicide layer.

Abstract: A mask structure may include a first mask pattern and a second mask pattern formed on an object. When the object includes a first material, the first and the second mask patterns may include a second material and a third material, respectively. The second mask pattern may have at least two openings that expose portions of the object adjacent to sides of the first mask pattern. Because the mask structure has the first and the second mask patterns, desired structures, for example, recesses, trenches, contact holes or patterns may be more precisely formed on or through the object. For example, the first mask pattern may protect the object in an etching process for forming contact holes so that the contact holes may not be connected to each other, for example, when the contact holes have bar shapes or line shapes.

Abstract: A method of manufacturing a pattern structure and a method of forming a trench using the same are provided. A mask pattern structure having mask patterns spaced apart from one another may be formed on a layer. The mask pattern structure may be divided into a first region having a first pattern density and a second region having a second pattern density higher than the first pattern density. The layer may be etched using the mask pattern structure as an etching mask to form first sidewalls positioned under the first region and second sidewalls positioned under the second region. The first sidewall may have a first profile that may be substantially vertical. The second sidewall may have a second profile of which an interval between the second sidewalls becomes narrower toward lower portions of the second sidewalls.

Abstract: A semiconductor device for reinforcing a substructure of a bond pad and a method for fabricating the same are provided. According to an embodiment, a semiconductor device for reinforcing a substructure of a bond pad comprises a semiconductor substrate and a substructure formed on the semiconductor substrate. The semiconductor device further includes an interlevel dielectric layer formed on the substructure. The interlevel dielectric layer includes a contact opening formed therein. The contact opening comprises a plurality of separate dots connected to each other. A contact plug is formed in the contact opening.

Abstract: A semiconductor device for reinforcing a substructure of a bond pad and a method for fabricating the same are provided. According to an embodiment, a semiconductor device for reinforcing a substructure of a bond pad comprises a semiconductor substrate and a substructure formed on the semiconductor substrate. The semiconductor device further includes an interlevel dielectric layer formed on the substructure. The interlevel dielectric layer includes a contact opening formed therein. The contact opening comprises a plurality of separate dots connected to each other. A contact plug is formed in the contact opening.