Patents by Inventor Jia-An Tsai

Jia-An Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133781
    Abstract: A kit for extracting mycotoxin residues in agricultural products according to the present disclosure includes a pipe, a first powder mixture layer and a second powder mixture layer. The pipe has an output port at the bottom thereof and an input port at the top thereof for inputting a sample solution. The first powder mixture layer is in the form of powder and filled in the pipe. The first powder mixture layer contains cation exchange resin powder, C18 and diatomaceous earth powder. The second powder mixture layer is in the form of powder and filled in the pipe. The second powder mixture layer is located below the first powder mixture layer and above the output port. The second powder mixture layer contains PSA powder, anhydrous magnesium sulfate powder, activated carbon, PLS powder, diatomaceous earth powder and C18 powder. The present disclosure further provides a method of obtaining a primary test liquid from agricultural products using the above kit.
    Type: Application
    Filed: June 5, 2023
    Publication date: April 25, 2024
    Inventors: HUNG-TA HUA, TSENG-YU TSAI, YI-JIA KU
  • Patent number: 11956938
    Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Kuan-Lun Cheng, Yasutoshi Okuno, Jiun-Jia Huang
  • Publication number: 20240113119
    Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Jiun-Jia Huang, Kuan-Lun Cheng, Chi-Hsing Hsu
  • Publication number: 20230081959
    Abstract: A system and a method for managing a virtual network function (VNF) and a multi-access edge computing (MEC) topology are provided. The method includes the following steps. A first VNF descriptor (VNFD) corresponding to a first VNF is received. According to the first VNFD, first provision data is generated. According to the first VNFD, first internal topology information of the first VNF is generated. According to the first provision data, the first VNF is instantiated to be provisioned. In response to provisioning the first VNF, a graphical user interface including the first internal topology information is output, and the first internal topology information includes a network component communicatively connected to the first VNF.
    Type: Application
    Filed: October 24, 2021
    Publication date: March 16, 2023
    Applicant: Chunghwa Telecom Co., Ltd.
    Inventors: Wen-Sheng Li, Si-An Ciou, Chi-Te Chiu, Chun-Hao Chen, Jia-An Tsai
  • Publication number: 20080278911
    Abstract: A cooling fan and dynamic pressure bearing structure is disclosed. The cooling fan includes a base portion, a bearing portion, a dynamic pressure bearing, a coil assembly, and an impeller assembly. The dynamic pressure bearing is received in the bearing portion. A plurality of pressure collecting grooves is arranged in an inner surface of a shaft hole of the dynamic pressure bearing at intervals for receiving lubricating oil. Each pressure collecting groove has two slanted grooves extending slantways which connect with each other at one end to form a connecting point. A transverse groove extends from the connecting point backward the direction of the two slanted grooves. Based on the special design of the pressure collecting groove, the present invention increases the area that creates pressure to increase the intensity of the pressure and decrease the number of pressure collecting grooves to reduce processing loads and production costs.
    Type: Application
    Filed: May 11, 2007
    Publication date: November 13, 2008
    Inventors: Wen-Pin Chen, Sheng-Pin Su, Zhen-Yu Lee, Meng-Jia Tsai, Mei-Lin Lai
  • Publication number: 20050089121
    Abstract: The present invention relates to a re-configurable Viterbi decoder. By re-setting the values of some registers, the inside control path and data path of the Viterbi decoder can be appropriately changed so as to meet the requirements of different communication systems. The Viterbi decoder comprises a branch metric calculator for receiving data items to be decoded and calculating the branch metrics; an add-compare-select unit for performing an add-compare-select operation on the output of the branch metric calculator and the corresponding path metric; a path metric storage unit (PMS unit) for saving a new path metric produced by the add-compare-select operation in an in-place way; a path memory for storing the shifted out selection bit after the add-compare-select operation; and a trace back unit for reading the selection bit of the path memory so as to perform the feedback decoding.
    Type: Application
    Filed: May 19, 2004
    Publication date: April 28, 2005
    Applicant: Industrial Technology Research Institute
    Inventors: Jia Tsai, Hung Lai, Jian Shen
  • Patent number: 5893740
    Abstract: A method of forming a short channel field effect transistor is disclosed. The method includes the steps of providing a semiconductor substrate having a well region of a first conductivity type; forming a gate electrode on the well region; implanting first impurities into the well region and adjacent to the gate electrode, the first implant step being at a first dose and a second conductivity type; forming sidewall spacers on edges of the gate electrode; implanting second impurities into the well region and adjacent to the gate electrode, the second implant step being at a second dose and at the second conductivity type; and implanting third impurities into the well region and adjacent the gate electrode, the third implant step being at a third dose and at the first conductivity type.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: April 13, 1999
    Assignee: National Science Council
    Inventors: Chun-Yeh Chang, I-Feng Tseng, Jaw-Jia Tsai