Patents by Inventor Jia-Chang LIN

Jia-Chang LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009410
    Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu
  • Patent number: 11996481
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Patent number: 11979158
    Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yu Lin, Yung-Chen Chien, Jia-Hong Gao, Jerry Chang Jui Kao, Hui-Zhong Zhuang
  • Patent number: 11978802
    Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Wei Hsu, Chih-Hao Wang, Huan-Chieh Su, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu
  • Publication number: 20240088145
    Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Chih-Hao Wang, Kuo-Cheng Ching
  • Patent number: 9860930
    Abstract: An electronic device includes a processor and a wireless communication module, The processor transmits one or more touch link messages via at least one transmitting electrode of a touch panel device to another electronic device in proximity to the electronic device and receives one or more touch link messages via at least one receiving electrode of the touch panel device from the other electronic device to obtain essential information for establishing a wireless communication connection with the other electronic device. The wireless communication module establishes a wireless communication connection with the other electronic device according to the essential information.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: January 2, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tsung-Yueh Chiang, Jia-Chang Lin, Jing-Kuang Huang, Yu-Chieh Chien
  • Publication number: 20160345372
    Abstract: An electronic device includes a processor and a wireless communication module, The processor transmits one or more touch link messages via at least one transmitting electrode of a touch panel device to another electronic device in proximity to the electronic device and receives one or more touch link messages via at least one receiving electrode of the touch panel device from the other electronic device to obtain essential information for establishing a wireless communication connection with the other electronic device. The wireless communication module establishes a wireless communication connection with the other electronic device according to the essential information.
    Type: Application
    Filed: February 17, 2015
    Publication date: November 24, 2016
    Inventors: Tsung-Yueh CHIANG, Jia-Chang LIN, Jing-Kuang HUANG, Yu-Chieh CHIEN
  • Publication number: 20090135584
    Abstract: A light emitting module includes a back plate, at least one fluorescent lamp, a circuit board and a transforming unit. The fluorescent lamp is disposed on a surface of the back plate and has an electrode wire. The circuit board is disposed on the other surface of the back plate. The transforming unit is disposed on the circuit board and has at least one pin. The electrode wire connects with the pin directly.
    Type: Application
    Filed: November 19, 2008
    Publication date: May 28, 2009
    Inventor: Jia-Chang LIN