Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common polysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common polysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common polysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common polysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common polysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common polysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common ploysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common ploysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common ploysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first Mag., followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Abstract: A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first magnification, followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common ploysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common ploysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common ploysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first Mag., followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Abstract: A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first Mag., followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Abstract: By introducing a carefully controlled anneal step after the deposition of tungsten silicide (onto a layer of polysilicon) but before the deposition of a layer of silicon oxide, interaction between the tungsten silicide and a subsequently deposited layer of silicon oxide is greatly reduced or eliminated. This gives good values for the resistance of gate lines formed from the composite as well as for the contact resistance between the polysilicon and the tungsten silicide.