Abstract: Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode, and the semiconductor nanostructures are adjacent to an epitaxial structure. The method also includes recessing the gate dielectric layer, and a protruding portion of the gate electrode protrudes from a top surface of the gate dielectric layer after the gate dielectric layer is recessed. The method further includes forming a protective structure over the epitaxial structure, and the protective structure laterally surrounds the protruding portion of the gate electrode. In addition, the method includes forming a conductive contact electrically connected to the epitaxial structure and penetrating through the protective structure.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure and a second gate stack over the second channel structure. The first gate stack and the second gate stack have a first work function layer and a second work function layer, respectively. The first work function layer and the second work function layer are made of a same material. The second gate stack has a first protruding portion and a second protruding portion, and each of the first protruding portion and the second protruding portion extends upwards and extend away from the second channel structure. The first protruding portion and the second protruding portion are spaced apart from each other, and half of the first gate stack is wider than the first protruding portion.

Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.

Abstract: A device includes a channel region, a gate structure, first and second gate spacers, and first and second dielectric liners. The gate structure is over the channel region. The epitaxial structure interfaces a sidewall of the channel region. An inner sidewall of the first gate spacer has a lower region interfacing a first side of the gate structure. An inner sidewall of the second gate spacer has a lower region interfacing a second side of the gate structure. A first dielectric liner interfaces an upper region of the inner sidewall of the first gate spacer. A second dielectric liner interfaces an upper region of the inner sidewall of the second gate spacer. The second dielectric liner is separated from the first dielectric liner in a cross-sectional view.

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

Abstract: A semiconductor device includes first channel members, a first gate structure wrapping around each of the first channel members, a first epitaxial feature abutting the first channel members, second channel members, a second gate structure wrapping around each of the second channel members, a second epitaxial feature abutting the second channel members, and an isolation feature has a first portion laterally stacked between the first and second gate structures and a second portion laterally stacked between the first and second epitaxial features. A width of the first portion of the isolation feature is larger than a width of the second portion of the isolation feature.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

Abstract: A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first di electric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.

Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.

Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures. The semiconductor nanostructures are beside an epitaxial structure. The method includes forming a dielectric layer over the metal gate stack and the epitaxial structure. The method further includes forming a contact opening in the dielectric layer and forming a protective layer over sidewalls of the contact opening. In addition, the method includes deepening the contact opening so that the contact opening extends into the epitaxial structure after the formation of the protective layer. The method includes forming a conductive contact filling the contact opening.

Abstract: An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.

Abstract: An integrated circuit includes a nanosheet transistor having a plurality of stacked channels, a gate electrode surrounding the stacked channels, a source/drain region, and a source/drain contact. The integrated circuit includes a first dielectric layer between the gate metal and the source/drain contact, a second dielectric layer on the first dielectric layer, and a cap metal on the first gate metal and on a hybrid fin structure. The second dielectric layer is on the hybrid fin structure between the cap metal and the source/drain contact.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a dielectric wall disposed over a substrate, first and second metal gate structure portions respectively disposed at either side of the dielectric wall. Each first and second metal gate structure portion includes a plurality of semiconductor layers vertically stacked and separated from each other, a high-K (HK) dielectric layer disposed to surround at least three surfaces of each of the semiconductor layers, and a gate electrode layer disposed between two neighboring semiconductor layers. The semiconductor device structure also includes a metal layer disposed on two opposing sidewalls of the dielectric wall.