Patents by Inventor Jia Fang Wu

Jia Fang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple-level interconnect structure and manufacturing method thereof
    Patent number: 12255111
    Abstract: Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 18, 2025
    Assignee: United Microelectronics Corp.
    Inventors: Jia Fang Wu, Hsiang-Chieh Yen, Hsu-Sheng Huang, Zhi Jian Wang
  • MULTIPLE-LEVEL INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220415724
    Abstract: Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.
    Type: Application
    Filed: August 4, 2021
    Publication date: December 29, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Jia Fang Wu, Hsiang-Chieh Yen, Hsu-Sheng Huang, Zhi Jian Wang