Patents by Inventor Jia-Fu Lin
Jia-Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145163Abstract: A transformer includes a bobbin and a plurality of coils wound on the bobbin. The plurality of coils includes a first primary coil; a second primary coil, located above the first primary coil and electrically connected to the first primary coil; a secondary coil, located between the first primary coil and the second primary; a first auxiliary coil, located above the second primary coil; and a second auxiliary coil, located on the first auxiliary coil and electrically connected to the first auxiliary coil.Type: ApplicationFiled: October 20, 2023Publication date: May 2, 2024Inventors: Chiao FU, Yi-Chao LIN, Yao-Zhong LIU, Jia-Tay KUO
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Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
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Patent number: 10128368Abstract: A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.Type: GrantFiled: January 13, 2016Date of Patent: November 13, 2018Assignee: SINOPOWER SEMICONDUCTOR, INC.Inventors: Po-Hsien Li, Jia-Fu Lin, Chia-Cheng Chen, Wei-Chieh Lin
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Patent number: 9991378Abstract: A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.Type: GrantFiled: June 20, 2016Date of Patent: June 5, 2018Assignee: SINOPOWER SEMICONDUCTOR, INC.Inventors: Po-Hsien Li, Wei-Chieh Lin, Jia-Fu Lin, Guo-Liang Yang
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Patent number: 9929702Abstract: A multi-stage Radio Frequency (RF) power amplifier is presented herein. According to one embodiment, the amplifier comprises: a first amplification stage configured to amplify an input signal to provide a first output signal having a phase distortion; a second amplification stage having an input and configured to amplify the first output signal that is received at the input to provide a second output signal, wherein the second output signal has a carrier frequency (FC) modulated by a signal content (S) having a signal content bandwidth (FS); and a resonant circuit comprising an inductor and a capacitor and having a resonant frequency (FR), the resonant circuit coupled to the input of the second amplification stage and compensating for the phase distortion caused by the first amplification stage at frequencies within the signal content bandwidth FS, wherein the resonant frequency FR is less than the signal content bandwidth FS.Type: GrantFiled: September 14, 2016Date of Patent: March 27, 2018Assignee: Qorvo US, Inc.Inventors: Wenlong Ma, Barry Jia-Fu Lin
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Publication number: 20170365708Abstract: A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.Type: ApplicationFiled: June 20, 2016Publication date: December 21, 2017Inventors: PO-HSIEN LI, WEI-CHIEH LIN, JIA-FU LIN, GUO-LIANG YANG
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Patent number: 9799743Abstract: A trenched power semiconductor element, a trenched-gate structure thereof being in an element trench of an epitaxial layer and including at least a shielding electrode, a shielding dielectric layer, a gate electrode, an insulating separation layer, and a gate insulating layer. The shielding electrode is disposed at the bottom of the element trench, the shielding dielectric layer is disposed at a lower portion of the element trench, surrounding the shielding electrode to separate the shielding electrode from the epitaxial layer, wherein the top portion of the shielding dielectric layer includes a hole. The gate electrode is disposed above the shielding electrode, being separated from the hole at a predetermined distance through the insulating separation layer. The insulating separation layer is disposed between the shielding dielectric layer and the gate electrode layer to seal the hole.Type: GrantFiled: November 22, 2016Date of Patent: October 24, 2017Assignee: SINOPOWER SEMICONDUCTOR, INC.Inventors: Po-Hsien Li, Guo-Liang Yang, Wei-Chieh Lin, Jia-Fu Lin
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Patent number: 9722071Abstract: A trench power transistor is provided. The trench gate structure of the trench power transistor includes at least one insulting layer, a gate electrode, and a shielding electrode, which are disposed in a trench of an epitaxial layer. The insulating layer formed on an inner wall of the active trench to isolate an epitaxial layer from the gate and the shielding electrodes. The insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The first and second dielectric layers extend from an upper portion of the inner wall to a lower portion of the inner wall of the active trench. The third dielectric layer is formed on the second dielectric layer and located at the lower portion of the active trench. A portion of the second dielectric layer is interposed between the first and third dielectric layers.Type: GrantFiled: January 25, 2016Date of Patent: August 1, 2017Assignee: SINOPOWER SEMICONDUCTOR, INC.Inventors: Po-Hsien Li, Guo-Liang Yang, Jia-Fu Lin, Wei-Chieh Lin
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Publication number: 20170213906Abstract: A trench power transistor is provided. The trench gate structure of the trench power transistor includes at least one insulting layer, a gate electrode, and a shielding electrode, which are disposed in a trench of an epitaxial layer. The insulating layer formed on an inner wall of the active trench to isolate an epitaxial layer from the gate and the shielding electrodes. The insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The first and second dielectric layers extend from an upper portion of the inner wall to a lower portion of the inner wall of the active trench. The third dielectric layer is formed on the second dielectric layer and located at the lower portion of the active trench. A portion of the second dielectric layer is interposed between the first and third dielectric layers.Type: ApplicationFiled: January 25, 2016Publication date: July 27, 2017Inventors: PO-HSIEN LI, GUO-LIANG YANG, JIA-FU LIN, WEI-CHIEH LIN
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Publication number: 20170200822Abstract: A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: PO-HSIEN LI, JIA-FU LIN, CHIA-CHENG CHEN, WEI-CHIEH LIN
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Publication number: 20170077879Abstract: A multi-stage Radio Frequency (RF) power amplifier is presented herein. According to one embodiment, the amplifier comprises: a first amplification stage configured to amplify an input signal to provide a first output signal having a phase distortion; a second amplification stage having an input and configured to amplify the first output signal that is received at the input to provide a second output signal, wherein the second output signal has a carrier frequency (FC) modulated by a signal content (S) having a signal content bandwidth (FS); and a resonant circuit comprising an inductor and a capacitor and having a resonant frequency (FR), the resonant circuit coupled to the input of the second amplification stage and compensating for the phase distortion caused by the first amplification stage at frequencies within the signal content bandwidth FS, wherein the resonant frequency FR is less than the signal content bandwidth FS.Type: ApplicationFiled: September 14, 2016Publication date: March 16, 2017Inventors: Wenlong Ma, Barry Jia-Fu Lin
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Patent number: 9190384Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.Type: GrantFiled: March 20, 2014Date of Patent: November 17, 2015Assignee: TriQuint Semiconductor, Inc.Inventors: Shixi Louis Liu, Wenlong Ma, Frank Hin-Fai Chau, Barry Jia-Fu Lin
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Publication number: 20140206149Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.Type: ApplicationFiled: March 20, 2014Publication date: July 24, 2014Applicant: TriQuint Semiconductor, Inc.Inventors: Shixi Louis Liu, Wenlong Ma, Frank Hin-Fai Chau, Barry Jia-Fu Lin
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Patent number: 8718720Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.Type: GrantFiled: July 30, 2010Date of Patent: May 6, 2014Assignee: TriQuint Semiconductor, Inc.Inventors: Shixi Louis Liu, Wenlong Ma, Frank Hin-Fai Chau, Barry Jia-Fu Lin
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Patent number: 8680609Abstract: A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.Type: GrantFiled: April 21, 2011Date of Patent: March 25, 2014Assignee: Sinopower Semiconductor Inc.Inventors: Wei-Chieh Lin, Jia-Fu Lin
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Patent number: 8487705Abstract: Embodiments of circuits, apparatuses, and systems for a protection circuit to protect against overdrive or overvoltage conditions. Other embodiments may be described and claimed.Type: GrantFiled: May 24, 2011Date of Patent: July 16, 2013Assignee: TriQuint Semiconductor, Inc.Inventors: Jingshi Yao, Peter Hu, Xiaopeng Sun, Barry Jia-Fu Lin, Mehra Mokalla
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Patent number: 8319284Abstract: A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.Type: GrantFiled: July 20, 2010Date of Patent: November 27, 2012Assignee: Sinopower Semiconductor Inc.Inventors: Wei-Chieh Lin, Ho-Tai Chen, Jia-Fu Lin, Po-Hsien Li
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Patent number: 8198684Abstract: A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.Type: GrantFiled: November 8, 2009Date of Patent: June 12, 2012Assignee: Anpec Electronics CorporationInventors: Wei-Chieh Lin, Guo-Liang Yang, Jen-Hao Yeh, Jia-Fu Lin
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Publication number: 20120139037Abstract: A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.Type: ApplicationFiled: April 21, 2011Publication date: June 7, 2012Inventors: Wei-Chieh Lin, Jia-Fu Lin
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Patent number: 8178923Abstract: A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.Type: GrantFiled: July 20, 2010Date of Patent: May 15, 2012Assignee: Sinopower Semiconductor Inc.Inventors: Wei-Chieh Lin, Guo-Liang Yang, Jia-Fu Lin, Shian-Hau Liao