Abstract: Disclosed herein a system having an artificial intelligence model, which is executed to generate and display valuation reports on an interactive graphical user interface. The valuation reports include valuation information of companies. The valuation reports include multiple variables associated with the valuation information of the companies whose values are dynamic, and the values may be updated in real-time. The swift turnaround time of the valuation reports on the interactive graphical user interface may allow the client user to trade swiftly and efficiently.

Abstract: Provided herein is a nanopore structure, which in one aspect is a “carbon nanotube porin”, that comprises a short nanotube with an associated lipid coating. Also disclosed are compositions and methods enabling the preparation of such nanotube/lipid complexes. Further disclosed is a method for therapeutics delivery that involves a drug delivery agent comprising a liposome with a NT loaded with a therapeutic agent, introducing the therapeutic agent into a cell or a tissue or an organism; and subsequent release of the therapeutic agents into a cell.

Abstract: Provided herein is a nanopore structure, which in one aspect is a “carbon nanotube porin”, that comprises a short nanotube with an associated lipid coating. Also disclosed are compositions and methods enabling the preparation of such nanotube/lipid complexes. Further disclosed is a method for therapeutics delivery that involves a drug delivery agent comprising a liposome with a NT loaded with a therapeutic agent, introducing the therapeutic agent into a cell or a tissue or an organism; and subsequent release of the therapeutic agents into a cell.

Abstract: Systems and methods for collecting and aggregating data from multiple data sources on a real-time basis in an organized manner that can be stored, distributed, published, analyzed, and retrieved in various different formats and for different purposes is described. The methods include providing a user with reports and insights created by consolidating all data records and activity into a single data record generated by a common data model.

Abstract: This invention belongs to the field of biotechnology, in particular to a mutant double-strand DNA (dsDNA) helicase protein nanopore derived from bovine papillomavirus and its application. The technical problem to be solved by this invention is to overcome the deficiency that the existing small-diameter protein nanopore requires an external strength or component to transport dsDNA. The technical scheme in this invention to solve the above deficiency is to provide a truncated E1-1 (306-577) protein, an E1-2 (306-605) protein and its variant derived from bovine papillomavirus double-stranded DNA helicase protein, as well as a variant of its homologous protein which is used for preparing membrane containing conductive channel, providing a new and effective choice for this field.

Abstract: Provided herein is a nanopore structure, which in one aspect is a “carbon nanotube porin”, that comprises a short nanotube with an associated lipid coating. Also disclosed are compositions and methods enabling the preparation of such nanotube/lipid complexes. Further disclosed is a method for therapeutics delivery that involves a drug delivery agent comprising a liposome with a NT loaded with a therapeutic agent, introducing the therapeutic agent into a cell or a tissue or an organism; and subsequent release of the therapeutic agents into a cell.

Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.

Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.

Abstract: A carry-skip one-bit full adder and a field programmable gate array device, the full adder includes: a first multiplexer, a second multiplexer, and an adder, the first multiplexer includes a first addend input end and a first constant input end configured to input a first constant to the first multiplexer; the second multiplexer includes a second addend input end and a second constant input end configured to input a second constant to the second multiplexer; when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input, and the second multiplexer selects to output the second constant input.

Abstract: A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.

Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.

Abstract: A carry-skip one-bit full adder and a field programmable gate array device, the full adder includes: a first multiplexer, a second multiplexer, and an adder, the first multiplexer includes a first addend input end and a first constant input end configured to input a first constant to the first multiplexer; the second multiplexer includes a second addend input end and a second constant input end configured to input a second constant to the second multiplexer; when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input, and the second multiplexer selects to output the second constant input.

Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.

Abstract: A simulation verification method for Field Programmable Gate Array (FPGA) function modules and a system thereof. The method includes: generating all test cases by enumerating all parameter characteristics of FPGA function modules; generating, according to an input type and input parameter characteristics of an FPGA function module under test, a simulation test bench matching configuration of the corresponding FPGA function module under test; and randomly generating, by the simulation test bench, a test stimulus and a corresponding expected output according to the input parameter characteristics of the FPGA function module under test, comparing the expected output with an actual output obtained after the test stimulus is applied to the test case corresponding to the FPGA function module under test, and outputting a test report of the FPGA function module under test according to a comparison result.

Abstract: A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.

Abstract: An extensible and configurable logic element, wherein the logic element includes: multiple logic parcels, each logic parcel includes two logic cells; each logic cell includes seven inputs, three outputs, an addition carry input, an addition carry output, a six-input and two-output look-up table, a one bit full adder, a first register, and a second register; wherein, the first register stores a signal output by the first output of the look-up table or a carry signal of the full adder according to the configuration; the second register stores a signal output by the second output of the look-up table or an output signal of the full adder according to the configuration; the addition carry output in the current logic cell is connected to the addition carry input in the higher logic cell of the current logic cell, including an addition carry chain in the logic element.