Abstract: A multi-wavelength multi-port laser and router. By arranging a reflective facet at one end of the port-selection semiconductor optical amplifier and a partial reflector at one end of the wavelength-selection semiconductor optical amplifier, and cooperating with the intra-cavity wavelength router to form N×N optical resonant cavities, so that each optical resonant cavity can only emit the wavelength corresponding to the lowest round-trip loss between input and output ports. The extra-cavity wavelength router is mirrored with respect to the intra-cavity wavelength router, so that one or more wavelengths of light excited by any port-selection semiconductor optical amplifier can be transmitted from the corresponding output port of the extra-cavity wavelength router.

Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance ?D. The drain side wing of the gate contact is spaced apart from the barrier layer by a distance d1 that is equal to a thickness of the insulating layer. The distance ?D is less than about 0.3 ?m, and the distance d1 is less than about 80 nm.

Abstract: Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.

Abstract: A method for treating or preventing vascular endothelial cell injured diseases, especially cerebral infarctions or myocardial infarctions, by administering a c-MET agonist antibody to a subject in need thereof, and specific c-MET agonist antibodies.

Abstract: An analog-to-digital conversion method, an analog-to-digital converter and an image sensor, are provided. The analog-to-digital conversion method includes a first conversion period and a second conversion period; in the first conversion period and the second conversion period, a first counter and the second counter have different effective clock edges and work in a time-sharing way using the first count clock signal and the second count clock signal respectively; in the second conversion period, count directions of the first counter and the second counter are reversed, and the count results in the first conversion period are used as an initial value of the second conversion period; and the conversion result is output based on the first count result and the second count result.

Abstract: Provided herein are methods for multiplexed in situ analysis of biomolecules in a tissue. In particular, provided herein are methods for multiplexed single-cell in situ protein and nucleic acid profiling in fixed or fresh tissues, and also allows the investigation of the different cell compositions and their spatial organizations in intact tissues through consecutive cycles of probe hybridization, fluorescence imaging, and signal removal.

Abstract: Embodiments of pixel circuit, image sensor, image pickup device and methods for using the same are provided. In an example, the pixel circuit comprises a source module configured to output non-simultaneously a reference signal indicative of a reset level and an electrical signal indicative of incident light, a sampling module comprising a first sampling unit, a second sampling unit and a sampling switch, a first switch module configured to be electrically coupled between the source module and the sampling module, and a second switch module configured to be electrically coupled between the sampling module and a bus.

Abstract: Provided herein are high-throughput, high-quality methods of consecutive in situ hybridization for analysis of the genome and/or transcriptome in an individual cell with single-molecule sensitivity. In particular, provided herein are methods comprising visualizing individual genomic loci or transcripts as single detectable signals (e.g., fluorescent spots) which remain in place during consecutive hybridization. In each cycle of consecutive hybridization, detectably labeled probes hybridize to the probe used in the previous cycle, and also introduce the binding sites for the probe of the following cycle. Through consecutive cycles of probe hybridization, imaging, and signal removal, different genomic loci or RNA species can be identified by unique detectable signal profiles (e.g., fluorescent spots with unique color sequences). The number of varied color sequences increases exponentially with the number of hybridization cycles, which enables the genome or transcriptome-wide analysis.

Abstract: A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.

Abstract: An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

Abstract: A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.

Abstract: A data linking system is described herein that links data records corresponding to a particular real estate property even if there are inconsistencies in the data records, the physical presence of the real estate property has changed over time, and/or the data records use different terminology. In some cases the data records are matched using a trained machine learning model. The data linking system can optionally generate a visualization of the data record linkage via interactive user interfaces. By linking data records despite the issues described above, the data linking system reduces the number of navigational steps a user performs to obtain data associated with a property and/or reduces data processing times. The disclosed system may be used to generate and maintain a comprehensive database of substantially all properties within a jurisdiction, in which a unique identifier is assigned to each property.

Abstract: A device includes a substrate; a buffer layer on the substrate; a barrier layer on the buffer layer, a source electrically coupled to the barrier layer; a gate electrically coupled to the barrier layer; and a drain electrically coupled to the barrier layer. The device further includes an electron concentration reduction structure arranged with at least one of the following: in the barrier layer and on the barrier layer. The electron concentration reduction structure is configured to at least one of the following: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance.

Abstract: A transistor device includes a first unit subcell including having a first active region width extending in a first direction, and a second unit subcell having a second active region width extending in the first direction and arranged adjacent the first unit subcell in the first direction. The first unit subcell and the second unit subcell share a common drain contact and have separate gate contacts that are aligned in the first direction. Each unit subcell includes a field plate that is connected to a source contact outside the active region and that does not cross over the gate contact.

Abstract: Provided herein are methods for multiplexed in situ analysis of biomolecules in a tissue. In particular, provided herein are methods for multiplexed single-cell in situ protein and nucleic acid profiling in fixed or fresh tissues, that allows the investigation of the different cell compositions and their spatial organizations in intact tissues through consecutive cycles of probe hybridization, fluorescence imaging, and signal removal.

Abstract: A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The device includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the aperture in the surface dielectric layer, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced apart from the gate. A recessed portion of the multiple-stepped field plate is above the aperture in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent the recessed portion of the field plate on a side of the field plate opposite the gate, and a second step adjacent the first step.

Abstract: A method includes: The receive end receives 2N channels of signals through N first antennas, where the 2N channels of signals are respectively from N second antennas of the transmit end. When transmission performance of any one of the 2N channels of signals is less than a first threshold, the receive end respectively receives, from two second antennas, two channels of signals whose polarization directions are orthogonal. When transmission performance of the two channels of signals is both greater than a second threshold, the receive end receives the 2N channels of signals through the N first antennas.

Abstract: This invention provides a process for sequencing nucleic acids using 3? modified deoxynucleotide analogues or 3? modified deoxyinosine triphosphate analogues, and 3? modified dideoxynucleotide analogues having a detectable marker attached thereto.

Abstract: A gallium nitride-based RF transistor amplifier comprises a semiconductor layer structure comprising a barrier layer on a channel layer, first and second source/drain regions in the semiconductor layer structure, first and second source/drain contacts on the respective first and second source/drain regions, and a longitudinally-extending gate finger that is between the first and second source/drain contacts. The first and second source/drain contacts each has an inner sidewall that faces the gate finger and an opposed outer sidewall. The first source/drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure, and extends a second, smaller distance from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region.

Abstract: Provided in one or more embodiments of the description are an information importing method and apparatus. The method may comprise: a server receiving an information importing file uploaded by a user, wherein the information importing file includes information to be imported into a system; the server verifying the information included in the information importing file; the server marking information in the information importing file that does not pass the verification, so as to generate an error comparison file; and the server returning the error comparison file to the user.