Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A landmark identification and marking system for a panoramic image is provided. The system includes a storage device and a back-end processor. The storage device stores an initial panoramic image, attitude information, motion tracking information, and a landmark list. The back-end processor performs steps of: adjusting a visual angle of the initial panoramic image to a designated angle according to a difference value between the visual angle and the designated angle; providing the adjusted initial panoramic image to a front-end processor for calculating and generating a panoramic image integrated with landmark objects in the virtual space.

Abstract: An inductive position measuring sensor comprises a fixed ruler and a sliding ruler which can move relatively along the direction of the measuring axis. A series of coupling coils are made on the fixed ruler in the measuring direction,-two sets of driving coils are disposed on the sliding ruler, and induction coils in a staggered manner are also disposed on the sliding ruler. The two sets of driving coils generate excitation signals, by interaction with the coupling coils on the fixed ruler, and being received by the induction coils of the sliding ruler, they are used for measuring the relative movement of the fixed ruler and the sliding ruler. By controlling the positions and winding directions of the driving coils and the induction coils, the sensor can effectively inhibit the direct space signal interference of the driving coils to the induction coils, and the signal-to-noise ratio is improved.

Abstract: A service data processing method is provided, including: obtaining a target function and a constraint condition, where the constraint condition includes a constraint relationship between a plurality of variables, and the target function includes at least one variable of the plurality of variables; selecting an initial variable from the plurality of variables for a base variable group; sorting optimized values of variables in a non-base variable group to obtain a maximum heap structure, where each node in the maximum heap structure stores an identifier of a variable and an optimized value corresponding to the variable; updating the non-base variable group and the base variable group based on a first target variable; and obtaining a solving target of a service problem based on a variable in an updated base variable group and the constraint condition.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.

Abstract: A ship navigation display system is set in a ship and includes a communications device, sensing device, first computing device, second computing device and wearable device. The communications device receives first coordinate information corresponding to a ship. The sensing device senses second coordinate information corresponding to a first ship around the ship. The first computing device is communicably connected with the communications device and calculates a collision probability according to the first and second coordinate information. When the collision probability is greater than a threshold value, the first computing device transmits a collision prediction signal. The second computing device receives the collision prediction signal and projects the second coordinate information corresponding to the first ship to a virtual coordinate in a virtual space.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: The present disclosure provides a circuit board including a first circuit layer, a dielectric layer on the first circuit layer, and a seed layer on the dielectric layer and directly contacting the first circuit layer, in which a top surface of the seed layer includes a levelled portion. The circuit board also includes a second circuit layer on the levelled portion of the seed layer, in which a grain boundary density of the second circuit layer is lower than that of a portion of the seed layer directly contacting the first circuit layer.

Abstract: A Totem Pole PFC circuit includes at least one fast-switching leg, a slow-switching leg, and a control unit. Each fast-switching leg includes a fast-switching upper switch and a fast-switching lower switch. The slow-switching leg is coupled in parallel to the at least one fast-switching leg, and the slow-switching leg includes a slow-switching upper switch and a slow-switching lower switch. The control unit receives an AC voltage with a phase angle, and the control unit includes a current detection loop, a voltage detection loop, and a control loop. The control loop generates a second control signal assembly to respectively control the slow-switching upper switch and the slow-switching lower switch. The control loop controls the second control signal assembly to follow the phase angle, and dynamically adjusts a duty cycle of the second control signal assembly to turn on or turn off the slow-switching upper switch and the slow-switching lower switch.

Abstract: A terminal according to one aspect includes: at least one memory configured to store an instruction; and at least one processor configured to perform the instruction, wherein the processor performs the instruction, and thus provides, to another terminal, an authentication request related to data being an authentication target, authentication information about an own terminal, and credit information about the own terminal, acquires, from the another terminal, an authentication result of the another terminal for the authentication request, and reclaims the credit information from the another terminal or an authentication server after the another terminal accesses the authentication server and thus validity of the authentication information is authenticated.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode structure over a channel region, wherein the gate electrode structure includes a gate dielectric layer disposed over the first channel region, a gate electrode disposed over the gate dielectric layer, and insulating spacers disposed over opposing sidewalls of the gate electrode, wherein the gate dielectric layer is disposed over opposing sidewalls of the gate electrode. An interlayer dielectric layer is formed over opposing sidewalls of the insulating spacers. The insulating spacers are removed from an upper portion of the opposing sidewalls of the gate electrode to form trenches between the opposing sidewalls of the upper portion of the gate electrode and the interlayer dielectric layer, and the trenches are filled with an insulating material.

Abstract: A terminal according to one aspect includes: at least one memory configured to store an instruction; and at least one processor configured to perform the instruction, wherein the at least one processor performs the instruction, and thus provides an electronic signature to data by using a secret key of an own terminal, provides, as an authentication request to another terminal, the data provided with the electronic signature, acquires, from the another terminal, an authentication result of an authentication server for the authentication request, the authentication result being encoded by using a public key of the own terminal, and decodes the authentication result by using the secret key of the own terminal.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.