Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.

Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI.

Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.

Abstract: An activate circuit for an electronic device includes a first node, a first transistor including a source coupled to a ground, a drain coupled to the first node, and a gate coupled to a battery voltage, a first diode including an anode coupled to an activate signal, and a cathode a first resistance coupled between the cathode of the first diode and the first node, a capacitor coupled between the first node and the ground having a logic low level, and a second transistor including a source coupled to the ground, a drain coupled to the activate signal, and a gate coupled to the first node.

Abstract: An activate circuit for an electronic device includes a first node, a first transistor including a source coupled to a ground, a drain coupled to the first node, and a gate coupled to a battery voltage, a first diode including an anode coupled to an activate signal, and a cathode a first resistance coupled between the cathode of the first diode and the first node, a capacitor coupled between the first node and the ground having a logic low level, and a second transistor including a source coupled to the ground, a drain coupled to the activate signal, and a gate coupled to the first node.

Abstract: The present invention provides a fiber Bragg grating sensor system, which comprises a light-division device having receiving-sending terminals and sensing terminals, a light generating device and a photo detector coupled with receiving-sending terminal of a light-division device, sensing fibers coupled with the sensing terminals, said sensing fiber comprising a fiber Bragg grating, a information processor connecting with said photo detector. The light-division device distribute different optical energy ratio from said receiving-sending terminals to said sensing terminals. The intensity and wavelength division multiplexing can make different intensity for the information addressed of different sensing fiber on the same optical channel to enhance the sensing capacity of fiber Bragg grating sensor system.

Abstract: The present invention provides a fiber Bragg grating sensor system, which comprises a light-division device having receiving-sending terminals and sensing terminals, a light generating device and a photo detector coupled with receiving-sending terminal of a light-division device, sensing fibers coupled with the sensing terminals, said sensing fiber comprising a fiber Bragg grating, a information processor connecting with said photo detector. The light-division device distribute different optical energy ratio from said receiving-sending terminals to said sensing terminals. The intensity and wavelength division multiplexing can make different intensity for the information addressed of different sensing fiber on the same optical channel to enhance the sensing capacity of fiber Bragg grating sensor system.