Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

Abstract: A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.

Abstract: Systems and methods for an integrated circuit layout is disclosed. The integrated circuit layout includes a first block including multiple first cells, each of which has a first cell height, and a second block including multiple second cells, each of which has a second cell height. The first block is disposed next to the second block with a spacing that is either equal to zero or less than any of the first or second cell heights.

Abstract: A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.

Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

Abstract: Disclosed are a method and an apparatus for designing a magnetic shielding apparatus and a magnetic shielding apparatus. The method includes: determining a region of interest inside the magnetic shielding apparatus, the region of interest being a region where a magnetic shielding effect is expected to be achieved, and the magnetic shielding apparatus including N layers of shields disposed in a nested manner; determining a complete parameter set; and obtaining, based on the complete parameter set, a set of result parameters for describing the geometric structure, the set of result parameters that enables magnetic flux density in the region of interest to meet a preset threshold. This method not only greatly improves optimized magnetic shielding performance compared with an equal-spacing solution, but also resolves a problem that an analytical method cannot be used to optimize a magnetic shielding apparatus with a non-concentric structure.

Abstract: An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.

Abstract: An integrated circuit (IC) includes a first, second and third semiconductor cell regions. The first cell region includes a first active region having a first dopant type. The second semiconductor cell region abuts the first cell region in a second direction, and includes second and third active regions having correspondingly a second dopant type and the first dopant type. The second active region is between the first and third active regions. The third cell region abuts the second cell region in the second direction, and includes a fourth active region having the second dopant type. The third active region is between the fourth active region and the second active region. The second semiconductor cell region has a height 2H, and the first, second and third semiconductor cell regions collectively have a height 3H.

Abstract: A method for detecting an epileptic spike includes: obtaining, by a first module of a network model, a local feature of data to be detected, and obtaining, by a second module of the network model, a global feature of the data to be detected; and determining, by a third module of the network model, a detection result of whether there is the epileptic spike in the data to be detected according to the local feature and the global feature. The data to be detected contains a temporal domain and a spatial domain represented by multiple channels, the local feature is a single channel feature, and the global feature is a multichannel feature.

Abstract: A vision treatment system comprises a computer and a user input output module associated with the computer, the user input output module including a display screen and means for receiving user input, wherein the computer includes a testing and training module for one or more vision disorders, the training and testing module in communication with the user input output module and testing a user's cutoff spatial frequency of a contrast sensitivity and applying a training regimen based upon Perceptual Template Model (PTM) analysis of interactions with the user.

Abstract: A vision treatment system comprises a computer and a user input output module associated with the computer, the user input output module including a display screen and means for receiving user input, wherein the computer includes a testing and training module for one or more vision disorders, the training and testing module in communication with the user input output module and testing a user's cutoff spatial frequency of a contrast sensitivity and applying a training regimen based upon Perceptual Template Model (PTM) analysis of interactions with the user.

Abstract: In one embodiment, the present invention includes a method for performing magnetic resonance imaging on a subject and directly mapping electromagnetic activity of neural firing of the subject via the magnetic resonance imaging.

Abstract: In one embodiment, the present invention includes a method for performing magnetic resonance imaging on a subject and directly mapping electromagnetic activity of neural firing of the subject via the magnetic resonance imaging.