Abstract: A 3D image processing method, for processing a dynamic image region swapping between a first dynamic image gray level and a second dynamic image gray level, comprising: determining a max dynamic gray level reference value and a min dynamic gray level reference value, to generate an adjusted dynamic gray level and luminance curve; generating a dynamic table, which includes relations between the adjusted dynamic gray level and luminance curve, the first and second dynamic image gray level, according to the adjusted gray level and luminance curve; and adjusting the first and second dynamic image gray level according to the dynamic table.

Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract: A poly fuse trimming circuit. The poly fuse trimming circuit comprises a poly fuse and a silicon controlled rectifier (SCR) device. The poly fuse is coupled between a first fixed potential and an output node. The SCR device is controlled by a trimming signal and has an anode coupled to the output node and a cathode coupled to a second fixed potential.

Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract: A voltage regulator apparatus, wherein two transistors are coupled to an output terminal of a voltage regulator, so as to improve the transient response of output voltage and increase the stability of the output voltage. Besides, it avoids the use of an external capacitor.

Abstract: A poly fuse trimming circuit. The poly fuse trimming circuit comprises a poly fuse and a silicon controlled rectifier (SCR) device. The poly fuse is coupled between a first fixed potential and an output node. The SCR device is controlled by a trimming signal and has an anode coupled to the output node and a cathode coupled to a second fixed potential.

Abstract: A switched capacitor circuit of a pipeline analog to digital converter. The pipeline ADC includes a clock generator, a signal reference circuit, and a plurality of switched capacitor circuit. Each switched capacitor includes an operational amplifier, a first sampling capacitor, a first signal input switch, a first reference input switch, a first reference reset switch, and a first feedback network. A method for operating the switched capacitor circuit includes after the first reference input switch turning off, turning on the first signal input switch to transmit a first input signal to the first sampling capacitor and turning on the first reference reset switch to transmit a common signal to a second terminal of the first reference input switch, turning off the first reference rest switch then turning off the first signal input switch, and after the first signal input switch turning off, turning on the first reference input switch.

Abstract: A voltage regulator apparatus, wherein two transistors are coupled to an output terminal of a voltage regulator, so as to improve the transient response of output voltage and increase the stability of the output voltage. Besides, it avoids the use of an external capacitor.

Abstract: A successive approximation analog-to-digital converter is used for converting an analog input signal into a corresponding digital output signal. The successive approximation analog-to-digital converter has a successive approximation register for storing a first digital bit stream and a second digital bit stream that are related to the analog input signal, and a digital-to-analog converter for generating a first reference voltage and a second reference voltage according to the first and second digital bit streams. The digital-to-analog converter has a first voltage divider and a second voltage divider. The first voltage divider drives the first reference voltage approaching the analog input signal to establish the first digital bit stream, and the second voltage divider drives the second reference voltage approaching the analog input signal to establish the second digital bit stream. Finally, the first and second digital bit streams are averaged to generate the digital output signal.

Abstract: A voltage mode boost converter includes a control signal generating circuit, a step-up circuit, and a feedback circuit. The control signal generating circuit generates a step-up control pulse signal with a fixed period and a modulated amplitude. The step-up circuit adjusts an output voltage signal of the step-up circuit according to the step-up control pulse signal generated by the control signal generating circuit. The feedback circuit is electrically connected between the control signal generating circuit and the step-up circuit for generating a feedback voltage signal in accordance with the output voltage signal of the step-up circuit.

Abstract: A power converter includes a control signal generating circuit for generating a step-up control pulse signal with a fixed period and a modulated amplitude; a step-up circuit for adjusting an output voltage signal of the step-up circuit according to the step-up control pulse signal generated by the control signal generating circuit; and a feedback circuit, which is electrically connected to the control signal generating circuit and the step-up circuit, and which generates a feedback voltage signal according to the output voltage signal of the step-up circuit.

Abstract: Three diode structures on a metal-oxide-semiconductor (MOS) wafer. Each diode structure is capable of reducing parasitic current through the wafer and hence increasing the power conversion efficiency of a voltage step-up circuit.

Abstract: Three diode structures on a metal-oxide-semiconductor (MOS) wafer. Each diode structure is capable of reducing parasitic current through the wafer and hence increasing the power conversion efficiency of a voltage step-up circuit.