Abstract: An interposer, including a redistribution layer structure, first conductive terminals, and second conductive terminals, is provided. The first conductive terminals are disposed on a first surface and are electrically connected to the second conductive terminals. An orthographic projection area of the first conductive terminals on the redistribution layer structure is inside a circuit range outline. There is a first pitch between the adjacent first conductive terminals. The second conductive terminals are disposed on a second surface. An orthographic projection area of a first part of the second conductive terminals on the redistribution layer structure is inside the circuit range outline. An orthographic projection area of a second part of the second conductive terminals on the redistribution layer structure is outside the circuit range outline. There is a second pitch between the adjacent second conductive terminals. The second pitch is greater than the first pitch. A semiconductor package is also provided.

Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.

Abstract: A manufacturing method of a semiconductor packaging device is provided, and the manufacturing method includes steps as follows. A working chip is soldered on one surface of a wiring board so that an working circuit inbuilt inside a chip body of the working chip is electrically connected to the wiring board. A silicon thermal conductivity element is soldered on one surface of a heat-dissipating metal lid. The heat-dissipating metal lid is fixedly covered on the wiring board such that the silicon thermal conductivity element is sandwiched between the chip body and the heat-dissipating metal lid, and the silicon thermal conductivity element is electrically isolated from the working circuit of the chip body and the wiring board.

Abstract: An interposer, including a redistribution layer structure, first conductive terminals, and second conductive terminals, is provided. The first conductive terminals are disposed on a first surface and are electrically connected to the second conductive terminals. An orthographic projection area of the first conductive terminals on the redistribution layer structure is inside a circuit range outline. There is a first pitch between the adjacent first conductive terminals. The second conductive terminals are disposed on a second surface. An orthographic projection area of a first part of the second conductive terminals on the redistribution layer structure is inside the circuit range outline. An orthographic projection area of a second part of the second conductive terminals on the redistribution layer structure is outside the circuit range outline. There is a second pitch between the adjacent second conductive terminals. The second pitch is greater than the first pitch. A semiconductor package is also provided.

Abstract: A circuit board device includes a multilayer structure, a main ground area and a circuit module. The multilayer structure includes a plurality of plates. The main ground area is arranged in the multilayer structure. The circuit module includes a differential signal circuit and a surrounding circuit module. The differential signal circuit is located in the multilayer structure, and includes a positive signal pad and a negative signal pad. The positive signal pad is located on a configuration surface of one of the plates. The negative signal pad is located on the disposition surface, and is separated from the positive signal pad. The surrounding circuit module is located on the disposition surface, and electrically connected to the main ground area. The surrounding circuit module surrounds the positive signal pad and the negative signal pad in an enclosing way, and is physically separated from the differential signal circuit.

Abstract: A manufacturing method of a semiconductor packaging device is provided, and the manufacturing method includes steps as follows. A working chip is soldered on one surface of a wiring board so that an working circuit inbuilt inside a chip body of the working chip is electrically connected to the wiring board. A silicon thermal conductivity element is soldered on one surface of a heat-dissipating metal lid. The heat-dissipating metal lid is fixedly covered on the wiring board such that the silicon thermal conductivity element is sandwiched between the chip body and the heat-dissipating metal lid, and the silicon thermal conductivity element is electrically isolated from the working circuit of the chip body and the wiring board.

Abstract: A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board.

Abstract: A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board.

Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.

Abstract: A solid-state storage device includes a housing, a wiring board and a semiconductor package unit. The housing is formed with a heat-dissipating recess thereon. The wiring board is fixed in the housing. One side of the semiconductor package unit is mounted on the wiring board, and the other side of the semiconductor package unit is embedded in the heat-dissipating recess. A top surface and lateral surfaces surrounding the top surface of the semiconductor package unit are all thermally connected to the housing in the heat-dissipating recess.

Abstract: A solid-state storage device includes a housing, a wiring board and a semiconductor package unit. The housing is formed with a heat-dissipating recess thereon. The wiring board is fixed in the housing. One side of the semiconductor package unit is mounted on the wiring board, and the other side of the semiconductor package unit is embedded in the heat-dissipating recess. A top surface and lateral surfaces surrounding the top surface of the semiconductor package unit are all thermally connected to the housing in the heat-dissipating recess.

Abstract: A respirator (10) and a process of making the respirator (10) are disclosed. The respirator (10) can include a mask body (12) including right and left portions (16, 18) on each side of a centerline (14), where the right and left portions (16, 18) are bounded by a perimeter (24) of the mask body (12). The mask body (12) can also include a right tab (30) that extends from a right side perimeter segment (26) of the perimeter (24) of the mask body (12) adjacent the right portion (16), and a left tab (40) that extends from a left side perimeter segment (28) of the perimeter (24) of the mask body (12) adjacent the left portion (18); a right earloop (60) attached to the right tab (30) at first and second right attachment locations (50, 54); a left earloop (62) attached to the left tab (40) at first and second left attachment locations (52, 56); and a nose clip (92) disposed adjacent an upper perimeter segment (22) of the perimeter (24) of the mask body (12).

Abstract: A multilayer laminated substrate structure includes plural substrate layers stacked with each other, and a conductive via portion. One of the substrate layers is provided with a through hole. The conductive via portion includes a first signal conductive pad having a first rib, a second signal conductive pad having a second rib, and a conductive body which is disposed in the through hole and is electrically connected to the first rib and the second rib. The first signal conductive pad and the second signal conductive pad are disposed on two opposite surfaces of the substrate layer, and the first rib and the second rib are arranged in a staggered manner in relation to each other.

Abstract: A common-mode filter includes a first transmission line, a second transmission line, a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer includes a first conductive capacitor plate, in which at least partial first transmission line is in the first wiring layer, and electrically coupled with the first conductive capacitor plate. The second wiring layer includes a second conductive plate and a first inductor, and the second conductive capacitor plate is electrically coupled with the first inductor. The third wiring layer includes a third conductive capacitor plate, in which at least partial second transmission line is in the second wiring layer, and electrically coupled with the third conductive capacitor plate. The first conductive capacitor plate at least partial faces the second conductive capacitor plate, and the second conductive capacitor plate at least partial faces the third conductive capacitor plate.

Abstract: A multilayer laminated substrate structure includes plural substrate layers stacked with each other, and a conductive via portion. One of the substrate layers is provided with a through hole. The conductive via portion includes a first signal conductive pad having a first rib, a second signal conductive pad having a second rib, and a conductive body which is disposed in the through hole and is electrically connected to the first rib and the second rib. The first signal conductive pad and the second signal conductive pad are disposed on two opposite surfaces of the substrate layer, and the first rib and the second rib are arranged in a staggered manner in relation to each other.

Abstract: A common-mode filter includes a first transmission line, a second transmission line, a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer includes a first conductive capacitor plate, in which at least partial first transmission line is in the first wiring layer, and electrically coupled with the first conductive capacitor plate. The second wiring layer includes a second conductive plate and a first inductor, and the second conductive capacitor plate is electrically coupled with the first inductor. The third wiring layer includes a third conductive capacitor plate, in which at least partial second transmission line is in the second wiring layer, and electrically coupled with the third conductive capacitor plate. The first conductive capacitor plate at least partial faces the second conductive capacitor plate, and the second conductive capacitor plate at least partial faces the third conductive capacitor plate.

Abstract: A filter auto-calibration system comprises a multi-clock module that includes a multi-clock generator configured to generate a first variable frequency signal based on a channel setting, the multi-clock generator comprising a quadrature signal generator configured to generate an in-phase component and a quadrature component of the first variable frequency signal; and a mixer configured to generate an in-phase component and a quadrature component of a quadrature signal from a received signal other than the first variable frequency signal. The system also comprises at least one filter to be calibrated, and an auto-calibration control module coupled to the multi-clock module and the at least one filter, the auto-calibration control module configured to receive the in-phase component and quadrature component of the first variable frequency signal from the multi-clock module, and configured to control calibration of the at least one filter based on the channel setting.

Abstract: A filter auto-calibration system comprises a multi-clock module that includes a multi-clock generator configured to generate a first variable frequency signal based on a channel setting, the multi-clock generator comprising a quadrature signal generator configured to generate an in-phase component and a quadrature component of the first variable frequency signal; and a mixer configured to generate an in-phase component and a quadrature component of a quadrature signal from a received signal other than the first variable frequency signal. The system also comprises at least one filter to be calibrated, and an auto-calibration control module coupled to the multi-clock module and the at least one filter, the auto-calibration control module configured to receive the in-phase component and quadrature component of the first variable frequency signal from the multi-clock module, and configured to control calibration of the at least one filter based on the channel setting.

Abstract: A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module.

Abstract: An RC filter is calibrated to a desired cutoff frequency by initializing the filter with a cutoff frequency. An input signal is filtered by the RC filter to provide a filter output signal having phase and frequency values. The cutoff frequency of the RC filter is adjusted based on the phase and frequency values of the filter output signal if the phase and frequency values do not satisfy a predetermined condition. The filtering and adjusting are repeated until the phase and frequency values of the filter output signal satisfy the predetermined condition. A calibration apparatus has a frequency generator, a resistor-capacitor (RC) filter, a phase comparator, a frequency detector, and a state machine. The phase comparator, frequency detector, and state machine are configured to calibrate the RC filter to a cutoff frequency specified by the reference signal based on a filter output signal of the RC filter.