Patents by Inventor Jia-Lin Lo

Jia-Lin Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit device reliability simulation system
    Patent number: 9141735
    Abstract: The present disclosure provides systems for predicting semiconductor reliability. In an embodiment a method for predicting the semiconductor reliability includes receiving a degradation parameter input of a semiconductor device and using a degradation equation to determine a plurality of bias dependent slope values for degradation over a short time period according to the degradation parameter input. The plurality of slope values include at least two different slope values for degradation over time. The system accumulates the plurality of slope values and projects the accumulated slope values over a long time period to determine a stress effect for the semiconductor device.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Lin Lo, Ke-Wei Su, Min-Chie Jeng, Feng-Ling Hsiao, Cheng Hsiao, Yi-Shun Huang, Yi-Chun Chen
  • Constructing mapping between model parameters and electrical parameters
    Patent number: 8370774
    Abstract: A method includes determining a mapping between model parameters and electrical parameters of integrated circuits. The model parameters are configured to be used by a simulation tool. A set of electrical parameters is provided, and the mapping is used to map the set of electrical parameters to a set of model parameters.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: February 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ming Tsai, Ke-Wei Su, Cheng Hsiao, Min-Chie Jeng, Jia-Lin Lo, Feng-Ling Hsiao, Yi-Shun Huang
  • Constructing Mapping Between Model Parameters and Electrical Parameters
    Publication number: 20120054709
    Abstract: A method includes determining a mapping between model parameters and electrical parameters of integrated circuits. The model parameters are configured to be used by a simulation tool. A set of electrical parameters is provided, and the mapping is used to map the set of electrical parameters to a set of model parameters.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 1, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ming Tsai, Ke-Wei Su, Cheng Hsiao, Min-Chie Jeng, Jia-Lin Lo, Feng-Ling Hsiao, Yi-Shun Huang
  • CIRCUIT DEVICE RELIABILITY SIMULATION SYSTEM
    Publication number: 20110313735
    Abstract: The present disclosure provides systems for predicting semiconductor reliability. In an embodiment a method for predicting the semiconductor reliability includes receiving a degradation parameter input of a semiconductor device and using a degradation equation to determine a plurality of bias dependent slope values for degradation over a short time period according to the degradation parameter input. The plurality of slope values include at least two different slope values for degradation over time. The system accumulates the plurality of slope values and projects the accumulated slope values over a long time period to determine a stress effect for the semiconductor device.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 22, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ("TSMC")
    Inventors: Jia-Lin Lo, Ke-Wei Su, Min-Chie Jeng, Feng-Ling Hsiao, Cheng Hsiao, Yi-Shun Huang, Yi-Chun Chen