Patents by Inventor Jia Lin Yap

Jia Lin Yap has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9257403
    Abstract: An integrated circuit copper wire bond connection is provided having a copper ball (32) bonded directly to an aluminum bond pad (31) formed on a low-k dielectric layer (30) to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (Z1, Z2) located at an outer peripheral location (42) under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: February 9, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tu-Anh N. Tran, John G. Arthur, Yin Kheng Au, Chu-Chung Lee, Chin Teck Siong, Meijiang Song, Jia Lin Yap, Matthew J. Zapico
  • Publication number: 20150206829
    Abstract: A packaged semiconductor device has a lead frame, a semiconductor die, and bond wires. The lead frame has a two-dimensional array of leads with a subset of interior leads located in the interior of the array that do not extend to the perimeter of the array. The bond wires are connected to the semiconductor die and respective ones of the leads of the array.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Inventors: Yin Kheng Au, Seoh Hian Teh, Jia Lin Yap, Pey Fang Hiew, Ly Hoon Khoo
  • Publication number: 20150145148
    Abstract: An integrated circuit copper wire bond connection is provided having a copper ball (32) bonded directly to an aluminum bond pad (31) formed on a low-k dielectric layer (30) to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (Z1, Z2) located at an outer peripheral location (42) under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tu-Anh N. Tran, John G. Arthur, Yin Kheng Au, Chu-Chung Lee, Chin Teck Siong, Meijiang Song, Jia Lin Yap, Matthew J. Zapico
  • Publication number: 20150075849
    Abstract: A semiconductor device includes a lead frame having a flag and leads surrounding the flag. The flag includes a first die attach area and an interposer area. An insulated layer with at least one conductive trace is formed on the interposer area.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Inventors: Jia Lin Yap, Yin Kheng Au
  • Patent number: 8933547
    Abstract: A lead frame for a packaged semiconductor device has multiple, configurable power bars that can be selectively electrically connected, such as with bond wires, to each other and/or to other leads of the lead frame to customize the lead frame for different package designs. One or more of the configurable power bars may extend into one or more cut-out regions in a die paddle of the lead frame, which allows for short bond wires to be used to connect the power bars to die pads of a semiconductor die mounted on the die paddle.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jia Lin Yap, Yin Kheng Au, Ahmad Termizi Suhaimi, Seng Kiong Teng, Boon Yew Low, Navas Khan Oratti Kalandar
  • Publication number: 20140374151
    Abstract: A wire bonded electrical interconnection includes a first electrical contact, a second electrical contact, and a bond wire having a first end bonded to the first electrical contact, a second end bonded to the second electrical contact, and a central portion connecting the first and second ends. The central portion includes notches formed during a wire bonding process, with each notch having at least two corners.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventors: Jia Lin Yap, Poh Leng Eu, Ahmad Termizi Suhaimi
  • Publication number: 20140374467
    Abstract: A capillary bonding tool for wire bonding includes a first section, a second section and a bonding section. The first section has a first outer peripheral sidewall, an opposing first inner sidewall that extends generally parallel to the central longitudinal axis, and a first opening surrounded by the first inner sidewall. The second section has a second outer peripheral sidewall, an opposing second inner sidewall that extends at an angle with respect to the central longitudinal axis, and a second tapered opening surrounded by the second inner sidewall. The bonding section has a peripheral ridge extending axially outwardly from the second inner sidewall of the second section. The peripheral ridge has a third outer peripheral sidewall, a third inner tubular sidewall that extends generally parallel to the central longitudinal axis and radially outwardly of the first inner sidewall, and a third opening surrounded by the third inner tubular sidewall.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventors: Jia Lin Yap, Yin Kheng Au, Lai Cheng Law
  • Patent number: 8853840
    Abstract: A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yin Kheng Au, Pey Fang Hiew, Jia Lin Yap
  • Publication number: 20140263584
    Abstract: A method of making an electrical connection includes passing a bond wire through a wire bonding system having a wire polisher and a wire bonding tool. The wire polisher removes contamination from a first portion of the bond wire. A first bond is then formed by bonding the first portion of the bond wire to a first contact such that the bond wire and the first device are electrically connected. A second bond is then formed by bonding a second portion of the bond wire to a second contact such that the first contact and the second contact are electrically connected.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Inventors: Jia Lin Yap, Yin Kheng Au, Poh Leng Eu, Hung Yang Leong, Mohd Rusli Ibrahim, Navas Khan Oratti Kalandar, Mohd Faizal Zul-Kifli
  • Publication number: 20140231978
    Abstract: A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Inventors: Yin Kheng Au, Pey Fang Hiew, Jia Lin Yap