Patents by Inventor Jia Min Shieh

Jia Min Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11415457
    Abstract: The present invention provides a vibration sensor, which comprises a circuit board having an accommodating space. A sensing assembly is disposed in the accommodating space. A recess for magnet sliding is disposed in the sensing assembly. Dispose a magnet in the recess and then dispose a coil layer on an arbitrary side or both sides of the sensing assembly. Furthermore, a lubricating layer is coated on the recess. Alternatively, the recess can be a vacuum structure or a hollow cross-sectional structure for reducing the friction between the recess and the magnet. Alternatively, the coil layer can be coated with a protective layer or multiple layers can be stacked. Without increasing the area of the sensor, the sensing on the variation of magnetic flux can be improved. Accordingly, the vibration sensor according to the present invention can achieve wideband detection of vibrations.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 16, 2022
    Assignee: National Applied Research Laboratories
    Inventors: Yu-Sheng Lai, Jui-Min Liu, Hsu-Chun Cheng, Mei-I Li, Chun-Chi Chen, Cheng-San Wu, Jia-Min Shieh
  • Patent number: 10656129
    Abstract: The present invention provides a miniature gas sensor, which comprises a gas sensor chip. The gas sensor chip includes a hollow structure on the back. An insulating layer is disposed below the sensing material. A miniature heating device is disposed surrounding the sensing material. The sensing material is adhered to the sensing electrodes. The sensing material includes two metal oxide semiconductors or a compound structure of the sensing layer having a metal oxide semiconductor and a reaction layer with a rough surface. An interface layer is sandwiched between the two metal oxide layers for increasing the efficiency in sensing gas. The gas sensor according to the present invention can be implemented on silicon substrate with hollow structures. In addition, the size of the chip can be miniaturized.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 19, 2020
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Ting-Jen Hsueh, Yu-Jen Hsiao, Yu-Te Lin, Yen-Hsi Li, Yung-Hsiang Chen, Jia-Min Shieh
  • Patent number: 10600915
    Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: March 24, 2020
    Assignee: National Applied Research Laboratories
    Inventors: Wen-Hsien Huang, Jia-Min Shieh, Chang-Hong Shen
  • Patent number: 10533962
    Abstract: The present invention provides a gas sensor structure comprising a gas sensing chip. The back of the sensing material is a hollow structure. An insulating layer is below the sensing material. A micro heating is disposed surrounding the sensing material. The sensing material adheres to sensing electrodes. The sensing material is a complex structure including a metal oxide semiconductor and a roughened lanthanum-carbonate gas sensing layer. The thickness of the metal oxide semiconductor is between 0.2 ?m and 10 ?m; the thickness of the roughened lanthanum-carbonate gas sensing layer is between 0.1 ?m and 4 ?m; and the size of the back etching holes is smaller than 1*1 mm. By using the gas sensor structure according to the present invention, a suspended gas sensing structure can be fabricated on a silicon substrate and the chip size can be minimized.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 14, 2020
    Assignee: National Applied Research Laboratories
    Inventors: Yu-Jen Hsiao, Ting-Jen Hsueh, Yu-Te Lin, Yen-Hsi Li, Jia-Min Shieh, Chien-Wei Liu, Chi-Wei Chiang
  • Publication number: 20190360859
    Abstract: The present invention provides a vibration sensor, which comprises a circuit board having an accommodating space. A sensing assembly is disposed in the accommodating space. A recess for magnet sliding is disposed in the sensing assembly. Dispose a magnet in the recess and then dispose a coil layer on an arbitrary side or both sides of the sensing assembly. Furthermore, a lubricating layer is coated on the recess. Alternatively, the recess can be a vacuum structure or a hollow cross-sectional structure for reducing the friction between the recess and the magnet. Alternatively, the coil layer can be coated with a protective layer or multiple layers can be stacked. Without increasing the area of the sensor, the sensing on the variation of magnetic flux can be improved. Accordingly, the vibration sensor according to the present invention can achieve wideband detection of vibrations.
    Type: Application
    Filed: October 25, 2018
    Publication date: November 28, 2019
    Inventors: YU-SHENG LAI, JUI-MIN LIU, HSU-CHUN CHENG, MEI-I LI, CHUN-CHI CHEN, CHENG-SAN WU, JIA-MIN SHIEH
  • Patent number: 10446694
    Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 15, 2019
    Assignee: National Applied Research Laboratories
    Inventors: Kai-Shin Li, Bo-Wei Wu, Min-Cheng Chen, Jia-Min Shieh, Wen-Kuan Yeh
  • Publication number: 20190178860
    Abstract: The present invention provides a miniature gas sensor, which comprises a gas sensor chip. The gas sensor chip includes a hollow structure on the back. An insulating layer is disposed below the sensing material. A miniature heating device is disposed surrounding the sensing material. The sensing material is adhered to the sensing electrodes. The sensing material includes two metal oxide semiconductors or a compound structure of the sensing layer having a metal oxide semiconductor and a reaction layer with a rough surface. An interface layer is sandwiched between the two metal oxide layers for increasing the efficiency in sensing gas. The gas sensor according to the present invention can be implemented on silicon substrate with hollow structures. In addition, the size of the chip can be miniaturized.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: TING-JEN HSUEH, YU-JEN HSIAO, YU-TE LIN, YEN-HSI LI, YUNG-HSIANG CHEN, JIA-MIN SHIEH
  • Publication number: 20180358474
    Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 13, 2018
    Inventors: Kai-Shin Li, Bo-Wei Wu, Min-Cheng Chen, Jia-Min Shieh, Wen-Kuan Yeh
  • Publication number: 20180248044
    Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 30, 2018
    Inventors: WEN-HSIEN HUANG, JIA-MIN SHIEH, CHANG-HONG SHEN
  • Patent number: 9905547
    Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: February 27, 2018
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chang-Hong Shen, Jia-Min Shieh, Wen-Hsien Huang, Tsung-Ta Wu, Chih-Chao Yang, Tung-Ying Hsieh
  • Publication number: 20180038816
    Abstract: The present invention provides a gas sensor structure comprising a gas sensing chip. The back of the sensing material is a hollow structure. An insulating layer is below the sensing material. A micro heating is disposed surrounding the sensing material. The sensing material adheres to sensing electrodes. The sensing material is a complex structure including a metal oxide semiconductor and a roughened lanthanum-carbonate gas sensing layer. The thickness of the metal oxide semiconductor is between 0.2 ?m and 10 ?m; the thickness of the roughened lanthanum-carbonate gas sensing layer is between 0.1 ?m and 4 ?m; and the size of the back etching holes is smaller than 1*1 mm. By using the gas sensor structure according to the present invention, a suspended gas sensing structure can be fabricated on a silicon substrate and the chip size can be minimized.
    Type: Application
    Filed: December 6, 2016
    Publication date: February 8, 2018
    Inventors: YU-JEN HSIAO, TING-JEN HSUEH, YU-TE LIN, YEN-HSI LI, JIA-MIN SHIEH, CHIEN-WEI LIU, CHI-WEI CHIANG
  • Publication number: 20170110444
    Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Inventors: CHANG-HONG SHEN, JIA-MIN SHIEH, WEN-HSIEN HUANG, TSUNG-TA WU, CHIH-CHAO YANG, TUNG-YING HSIEH
  • Patent number: 9455350
    Abstract: A transistor device structure includes a substrate, a first polycrystalline semiconductor thin film and a first transistor unit. The first polycrystalline semiconductor thin film is disposed on the substrate. A grain diameter of the first polycrystalline semiconductor thin film is greater than 1 micrometer and a thickness of the first polycrystalline semiconductor thin film is less than three hundredths of the grain diameter. The first transistor unit is disposed on the first polycrystalline semiconductor thin film and includes a first gate dielectric layer and a first gate structure. The first gate dielectric layer is disposed on a surface of the first polycrystalline thin film semiconductor. The first gate structure is disposed on a surface of the first gate dielectric layer.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: September 27, 2016
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Jia-Min Shieh, Wen-Hsien Huang, Chang-Hong Shen, Chih-Chao Yang, Tung-Ying Hsieh
  • Patent number: 9281305
    Abstract: A transistor device structure includes a substrate, a first transistor layer and a second transistor layer. The second transistor layer is disposed between the substrate and the first transistor layer. The first transistor layer includes an insulating structure and a first transistor unit. The insulating structure is disposed on the second transistor layer and has a protruding portion. The first transistor unit includes a gate structure, a source/drain structure, an embedded source/drain structure and a channel. The source/drain structure is disposed beside the gate structure and over the insulating structure. The embedded source/drain structure is disposed underneath the source/drain structure and in the insulating structure. The channel is defined between the protruding portion and the gate structure.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: March 8, 2016
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chih-Chao Yang, Jia-Min Shieh, Wen-Hsien Huang, Tung-Ying Hsieh, Chang-Hong Shen, Szu-Hung Chen
  • Publication number: 20150280010
    Abstract: A transistor device structure includes a substrate, a first polycrystalline semiconductor thin film and a first transistor unit. The first polycrystalline semiconductor thin film is disposed on the substrate. A grain diameter of the first polycrystalline semiconductor thin film is greater than 1 micrometer and a thickness of the first polycrystalline semiconductor thin film is less than three hundredths of the grain diameter. The first transistor unit is disposed on the first polycrystalline semiconductor thin film and includes a first gate dielectric layer and a first gate structure. The first gate dielectric layer is disposed on a surface of the first polycrystalline thin film semiconductor. The first gate structure is disposed on a surface of the first gate dielectric layer.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 1, 2015
    Applicant: National Applied Research Laboratories
    Inventors: Jia-Min SHIEH, Wen-Hsien HUANG, Chang-Hong SHEN, Chih-Chao YANG, Tung-Ying HSIEH
  • Patent number: 9040333
    Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: May 26, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Jia-Min Shieh, Chang-Hong Shen, Wen-Hsien Huang, Bau-Tong Dai, Jung Y. Huang, Hao-Chung Kuo
  • Publication number: 20140264271
    Abstract: A ferroelectric memory device includes a memory layer, made of a silicon-based ferroelectric memory material. The silicon-based ferroelectric memory material includes a mesoporous silica film with nanopores and atomic polar structures on inner walls of the nanopores. The atomic polar structures are formed by asymmetrically bonding metal ions to silicon-oxygen atoms on the inner walls, and the silicon-based ferroelectric memory material includes semiconductor quantum dots, metal quantum dots and metal-semiconductor alloy quantum dots.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Jia-Min Shieh, Wen-Hsien Huang, Yu-Chung Lien, Chang-Hong Shen, Fu-Ming Pan, Hao-Chung Kuo
  • Publication number: 20140131716
    Abstract: A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate.
    Type: Application
    Filed: January 18, 2013
    Publication date: May 15, 2014
    Applicant: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Jia-Min Shieh, Yu-Chung Lien, Wen-Hsien Huang, Chang-Hong Shen, Min-Cheng Chen, Ci-Ling Pan
  • Publication number: 20140065754
    Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.
    Type: Application
    Filed: November 8, 2013
    Publication date: March 6, 2014
    Applicant: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Jia-Min SHIEH, Chang-Hong SHEN, Wen-Hsien HUANG, Bau-Tong DAI, Jung Y. HUANG, Hao-Chung KUO
  • Publication number: 20140008726
    Abstract: A semiconductor structure fabricating method includes the following steps. Firstly, a silicon substrate is provided. The silicon substrate has a first surface and a second surface. In addition, a first semiconductor structure is formed on the first surface of the silicon substrate. Then, the second surface of the silicon substrate is textured as a rough surface. Then, a first electrode layer is formed on the rough surface.
    Type: Application
    Filed: July 4, 2012
    Publication date: January 9, 2014
    Inventors: Yu-Jen HSIAO, Ting-Jen HSUEH, Jia-Min SHIEH, Yu-Ming YEH, Chee-Wee LIU, Bau-Tong DAI, Fu-Liang YANG