Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.

Abstract: A computing system with multiple processor cores manages power and performance by dynamic frequency scaling. The system detects a condition when a total number of active processor cores within one or more clusters is less than a predetermined number, and an operating frequency of the active processor cores has risen to a specified highest frequency. The system also obtains ambient temperature measurement of the one or more clusters. Upon detecting the condition, the system increases the operating frequency above the specified highest frequency based on the ambient temperature measurement while maintaining a same level of supply voltage to the active processor cores.

Abstract: This application provides a control method of a touch sensitive display apparatus, including the following steps: connecting to a first host and a second host via a network interface, and receiving a first picture and a second picture transmitted from the first host and the second host, respectively; displaying at least one part of the first picture and the second picture by a touch sensitive display interface, and receiving a touch sensitive control command corresponding to the displayed part of the first picture and the second picture; and in response to the touch sensitive control command received by the touch sensitive display interface, commanding the first host and the second host to perform a first operation and a second operation through the network interface, respectively.

Abstract: A computing system supports a clearance mode for its processor cores. The computing system can transition a target processor core from an active mode into a clearance mode according to a system policy. The system policy determines the number of processor cores to be in the active mode. The transitioning into the clearance mode includes the operations of migrating work from the target processor core to one or more other processor cores in the active mode in the computing system; and removing the target processor core from a scheduling configuration of the computing system to prevent task assignment to the target processor core. When the target processor core is in the clearance mode, the target processor core is maintained in an online idle state in which the target processor core performs no work.

Abstract: A mode switching handling method includes: when an operating system mode is switched from a first mode to a second mode, saving only a portion of register data that are stored in registers into a storage device, wherein an M-bit register length is used in the first mode, an N-bit register length is used in the second mode, and M and N are different integers.

Abstract: A method for operating an electronic device, and an electronic device, are provided. In the normal operation state of the electronic device, data which is stored in the main storage device of the electronic device is encrypted by a first encryption algorithm prior to being stored in a non-volatile storage device of the electronic device. The method includes the steps of generating snapshot data in the main storage device when the electronic device is entering a hibernation state, allocating space in the non-volatile storage device for storing the snapshot data, and storing the snapshot data in the space without encrypting the snapshot data using the first encryption algorithm.

Abstract: A CPU control method for controlling a first CPU and a second CPU The method comprises: (a) applying the first CPU to execute a first group of codes comprising at least one code if the first CPU is operating to perform a first function; and (c) applying the second CPU to execute a second group of codes comprising at least one code if the second CPU is operating to perform the first function. The first group of codes is optimized for the first CPU, the second group of codes is optimized for the second CPU and the first group of codes comprises at least one code different from the code for the second group of codes.

Abstract: Energy efficiency is managed in a multi-cluster system. The system detects an event in which a current operating frequency of an active cluster enters or crosses any of one or more predetermined frequency spots of the active cluster, wherein the active cluster includes one or more first processor cores. When the event is detected, the system performs the following steps: (1) identifying a target cluster including one or more second processor cores, wherein the each first processor core in the first cluster and each second processor core in the second cluster have different energy efficiency characteristics; (2) activating at least one second processor core in the second cluster; (3) determining whether to migrate one or more interrupt requests from the first cluster to the second cluster; and (4) determining whether to deactivate at least one first processor core of the active cluster based on a performance and power requirement.

Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

Abstract: The disclosure provides an electronic device including a coupler, a transceiver, and a control circuit. The coupler generates a coupled downlink signal according to a downlink signal from a head-end unit. The transceiver switches between the transmission of a downlink signal and the reception of an uplink signal according to a control signal. The control circuit receives the coupled downlink signal, generates a status counting signal according to the power status of the coupled downlink signal, and generates the control signal according to the status counting signal. Only when the level of the coupled downlink signal is lower than an amplitude threshold level with a duration longer than a status counting time, the control circuit converts the status counting signal from a first logic level to a second logic level opposite to the first logic level. Otherwise, the control circuit maintains the status counting signal on the first logic level.

Abstract: A technique, as well as select implementations thereof, pertaining to dynamic adjustment of speed of memory is described. The technique may involve obtaining information indicative of memory transactions associated with a memory device from an external memory interface coupled to the memory device. The technique may also involve determining a runtime bandwidth of the memory device according to the memory transactions. The technique may further involve comparing the runtime bandwidth of the memory device to at least one threshold bandwidth. The technique may additionally involve adjusting the speed of the memory device according to a result of the comparing.

Abstract: A multi-core processor system and a method for assigning tasks are provided. The multi-core processor system includes a plurality of processor cores, configured to perform a plurality of tasks, and each of the tasks is in a respective one of a plurality of scheduling classes. The multi-core processor system further includes a task scheduler, configured to obtain first task assignment information about tasks in a first scheduling class assigned to the processor cores, obtain second task assignment information about tasks in one or more other scheduling classes assigned to the processor cores, and refer to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores.

Abstract: A task scheduling method for a multi-core processor system includes at least the following steps: when a first task belongs to a thread group currently in the multi-core processor system, where the thread group has a plurality of tasks sharing same specific data and/or accessing same specific memory address(es), and the tasks comprise the first task and at least one second task, determining a target processor core in the multi-core processor system based at least partly on distribution of the at least one second task in at least one run queue of at least one processor core in the multi-core processor system, and dispatching the first task to a run queue of the target processor core.

Abstract: The method and the device for position detection with palm rejection are disclosed. The invention provides a sensor and a controller for controlling the sensor. The sensor includes a plurality of strips. The controller execute a first kind of position detection and a second kind of position detection on the sensor. The first kind of position detection identifies an ignored zone, and the second kind of position detection executes the position detection outside the ignored zone.

Abstract: A task scheduling method is applied to a heterogeneous multi-core system. The heterogeneous multi-core system has at least one first processor core and at least one second processor core. The task scheduling method includes: referring to task priorities of tasks of the heterogeneous processor cores to identify at least one first task of the tasks that belongs to a first priority task group, wherein each first task belonging to the first priority task group has a task priority not lower than task priorities of other tasks not belonging to the first priority task group; and dispatching at least one of the at least one first task to at least one run queue of at least one of the at least one first processor core.

Abstract: A task scheduling method is applied to a heterogeneous multi-core processor system. The heterogeneous multi-core processor system has at least one first processor core and at least one second processor core. The task scheduling method includes: referring to task priorities of tasks of the heterogeneous processor cores to identify at least one first task of the tasks that belongs to a first priority task group, wherein each first task belonging to the first priority task group has a task priority not lower than task priorities of other tasks not belonging to the first priority task group; and dispatching at least one of the at least one first task to at least one run queue of at least one of the at least one first processor core.

Abstract: The disclosure provides an electronic device including a coupler, a transceiver, and a control circuit. The coupler generates a coupled downlink signal according to a downlink signal from a head-end unit. The transceiver switches between the transmission of a downlink signal and the reception of an uplink signal according to a control signal. The control circuit receives the coupled downlink signal, generates a status counting signal according to the power status of the coupled downlink signal, and generates the control signal according to the status counting signal. Only when the level of the coupled downlink signal is lower than an amplitude threshold level with a duration longer than a status counting time, the control circuit converts the status counting signal from a first logic level to a second logic level opposite to the first logic level. Otherwise, the control circuit maintains the status counting signal on the first logic level.

Abstract: A method and the device for palm ignoring disclosed. The device comprises a plurality of strips intersecting each other to form a plurality of intersecting regions. A pair of strips intersecting on an intersecting region contact to each other on a contact point to form a depressed intersecting region. The depression depressed by the palm can be determined by comparing the total impedance of the depression with a threshold so as to be ignored.

Abstract: A device comprises a plurality of strips intersecting each other to form a plurality of intersecting regions. A pair of strips intersecting on an intersecting region contact to each other on a contact point to form a depressed intersecting region. The erroneously determined intersecting regions can be detected by comparing the contact points with the corresponding intersecting regions so as to provide the only correct contact points.

Abstract: A method and the device for position detection are disclosed. The device comprises a plurality of strips intersecting each other to form a plurality of intersecting regions. A pair of depressed strips intersecting on an intersecting region contact to each other to form a depressed intersecting region. According to the depressed intersecting regions, each depression can be determined. The total contact impedance of a depressing crossover a plurality of intersecting regions is the parallel contact impedance of the contact impedances of all intersecting regions corresponding to the same depression.