Abstract: In one aspect, the disclosure relates to a facile strategy to introduce electron-deficient aryl sulfate diesters to silylated hydroxyl groups of carbohydrates and amino acids, among other substrates, wherein selective hydrolysis and the removal of an electron-deficient aromatic group allows for the efficient generation of sulfated carbohydrates, peptides, and other compounds. The incorporation of electron-deficient aryl sulfate diesters in the early stage of the synthesis of glycans, peptides, and the like, disclosed herein avoids time-consuming protecting group manipulations, simplifies the purification of sulfated products, and improves the overall yield and efficiency. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.

Abstract: Radical cascade reactions enabling sequence-controlled ring-closing polymerization and ring-opening polymerization for the controlled synthesis of polymers with complex main-chain structures are provided. Facile syntheses leading to low-strain macrocyclic monomers consisting of the ring-opening triggers and extended main-chain structures are also provided. The present disclosure further provides methods for excellent control over polymer molecular weights and molecular weight distributions and high chain-end fidelity allows for the preparation of polymeric systems with well-defined architectures. Further provided are the general nature of the radical cascade-triggered transformations in polymer chemistry, and its application to the synthesis of polymers with diverse main-chain structural motifs with tailored functions. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.

Abstract: Radical cascade reactions enabling sequence-controlled ring-closing polymerization and ring-opening polymerization for the controlled synthesis of polymers with complex main-chain structures are provided. Facile syntheses leading to low-strain macrocyclic monomers consisting of the ring-opening triggers and extended main-chain structures are also provided. The present disclosure further provides methods for excellent control over polymer molecular weights and molecular weight distributions and high chain-end fidelity allows for the preparation of polymeric systems with well-defined architectures. Further provided are the general nature of the radical cascade-triggered transformations in polymer chemistry, and its application to the synthesis of polymers with diverse main-chain structural motifs with tailored functions. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.

Abstract: The disclosure is directed to methods and compositions for screening a library of aptamers for aptamers having a binding affinity to a target molecule. Specifically, non-natural nucleotides can be introduced onto aptamers immobilized on the surface of beads. The non-natural nucleotides can then be subsequently chemically modified to include additional binding agents. For example, copper-catalyzed azide-alkyne cycloaddition (CuAAC) reactions can be used to introduce a wide range of binding agents onto non-natural nucleotides on beads.

Abstract: Radical cascade reactions enabling sequence-controlled ring-closing polymerization and ring-opening polymerization for the controlled synthesis of polymers with complex main-chain structures are provided. Facile syntheses leading to low-strain macrocyclic monomers consisting of the ring-opening triggers and extended main-chain structures are also provided. The present disclosure further provides methods for excellent control over polymer molecular weights and molecular weight distributions and high chain-end fidelity allows for the preparation of polymeric systems with well-defined architectures. Further provided are the general nature of the radical cascade-triggered transformations in polymer chemistry, and its application to the synthesis of polymers with diverse main-chain structural motifs with tailored functions. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.

Abstract: An energy-absorbing rockbolt includes an anchorage structure, wherein two ends of the anchorage structure are respectively provided with a mixing blade and a threaded fastening section; a nut is screwed to the threaded fastening section; a plate is mounted at one end, which is close to the threaded fastening section, of the anchorage structure in a sleeving manner; one side of the plate abuts against the nut; the anchorage structure consists of first anchorage structure parts and second anchorage structure parts, wherein the second anchorage structure parts are arranged between two first anchorage structure parts; each of the second anchorage structure parts is an elliptical rod-shaped structure; a plurality of inwardly-concave arc-shaped grooves are formed in an outer wall of the second anchorage structure part in an axial direction, and a reinforcing rib is convexly formed at an intersection of two adjacent arc-shaped grooves.

Abstract: An M-type energy-absorbing rockbolt includes an anchorage structure, wherein two ends of the anchorage structure are respectively provided with a mixing blade and a threaded fastening section; a nut is screwed to the threaded fastening section; a plate is mounted at one end, which is close to the threaded fastening section, of the anchorage structure in a sleeving manner; one side of the plate abuts against the nut; the anchorage structure consists of first anchorage structure parts and second anchorage structure parts, wherein the second anchorage structure parts are arranged between two first anchorage structure parts; each of the second anchorage structure parts adopts an elliptical rod-shaped structure; a plurality of inwardly-concave arc-shaped grooves are formed in an outer wall of the second anchorage structure part in an axial direction, and a reinforcing rib is convexly formed at an intersection of two adjacent arc-shaped grooves.

Abstract: A computer program product for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Abstract: The present invention discloses a method for simulating a digital circuit comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.

Abstract: The present invention discloses a method for fixing hold time violations in circuits. The method comprises: creating a topology diagram of the circuit with a branch indicating a signal path where the hold time violation occurs in the circuit, and a node on the branch indicating a port of an element where the hold time violation occurs; dividing the circuit into a plurality of regions; and placing a hold time correction element selectively in a region corresponding to the node in the topology diagram to fix the hold time violation thereof, according to a circuit element density of the region corresponding to the node in the topology diagram. With this method there will be no new element in a region whose circuit element density is excessively large, and it is unnecessary to move an element which has been placed in the circuit and an input/output pin thereof.

Abstract: A computer program product for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Abstract: A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Abstract: A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Abstract: The present invention discloses a method for fixing hold time violations in circuits. The method comprises: creating a topology diagram of the circuit with a branch indicating a signal path where the hold time violation occurs in the circuit, and a node on the branch indicating a port of an element where the hold time violation occurs; dividing the circuit into a plurality of regions; and placing a hold time correction element selectively in a region corresponding to the node in the topology diagram to fix the hold time violation thereof, according to a circuit element density of the region corresponding to the node in the topology diagram. With this method there will be no new element in a region whose circuit element density is excessively large, and it is unnecessary to move an element which has been placed in the circuit and an input/output pin thereof.

Abstract: The present invention discloses a method for simulating a digital circuit. comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.

Abstract: The present invention relates to a method and an apparatus for estimating a clock skew. The method comprises: obtaining a basic clock skew of each clock tree in the circuit; judging whether two units are in a same clock domain; if they are in different clock domains, estimating the clock skew between units to be a larger one of basic clock skews of the clock trees corresponding to these two unit; if these two units are in the same clock domain, further judging whether they are in a same hierarchical logic block; if they are in different hierarchical logic blocks, estimating the clock skew between units to be the basic clock skew of the clock tree of these two units plus additional clock skew caused by different hierarchical logic blocks. The apparatus is corresponding to the method. With the method and apparatus, the clock skew in the circuit can be estimated more accurately, which improves the efficiency of circuit design.