Patents by Inventor Jia Nong
Jia Nong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934626Abstract: A joystick includes a stick head, an actuating component, a substrate, a bearing base, a resilient recovering component and a constraining component. The actuating component has a first end and a second end opposite to each other. The first end is connected to the stick head, and an identification feature is disposed on the second end. The substrate has a detection module used to detect the identification feature and determine motion of the stick head. The bearing base is disposed on the substrate. An opening portion of the bearing base aligns with the detection module and the actuating component. The resilient recovering component is disposed between the substrate and the bearing base. The constraining component is disposed on the resilient recovering component and movably disposed inside the opening portion, and used to abut against the actuating component in a detachable manner.Type: GrantFiled: June 20, 2022Date of Patent: March 19, 2024Assignee: PixArt Imaging Inc.Inventors: Hung-Yu Lai, Yong-Nong Huang, Hui-Hsuan Chen, Jia-Hong Huang
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Publication number: 20220354801Abstract: This disclosure relates to nanoparticles for preventing, treating and reversing atherosclerosis.Type: ApplicationFiled: March 24, 2022Publication date: November 10, 2022Inventors: Yinghui Zhong, Jia Nong, Zhicheng Wang
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Patent number: 11115036Abstract: An oscillator including a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal; a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage; a reference voltage generator configured to generate a reference voltage; an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal; a voltage controlled oscillator (VCO) configured to generate a first clock based on the frequency control signal; a frequency divider configured to frequency divide the first clock to generate a second clock; and a switched capacitor driver configured to generate the switched capacitor drive signal in response to the second clock. The oscillator may also include a switched capacitor sampler to sample the sawtooth or ramp voltage, wherein the filtered voltage is based on the sampled voltage.Type: GrantFiled: August 12, 2020Date of Patent: September 7, 2021Assignee: QUALCOMM INCORPORATEDInventors: Shitong Zhao, Kevin Jia-Nong Wang, Shyam Sivakumar, Debesh Bhatta
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Patent number: 10958279Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.Type: GrantFiled: September 6, 2019Date of Patent: March 23, 2021Assignee: QUALCOMM IncorporatedInventors: Debesh Bhatta, Kevin Jia-Nong Wang, Karthik Nagarajan, John Abcarius, Andrew Weil, Christian Venerus, Jeffrey Mark Hinrichs
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Publication number: 20210075434Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.Type: ApplicationFiled: September 6, 2019Publication date: March 11, 2021Inventors: Debesh BHATTA, Kevin Jia-Nong WANG, Karthik NAGARAJAN, John ABCARIUS, Andrew WEIL, Christian VENERUS, Jeffrey Mark HINRICHS
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Patent number: 10615808Abstract: An apparatus is disclosed that implements frequency synthesis with accelerated locking. In an example aspect, the apparatus includes an oscillating signal source, a modulus compensator, and a frequency generator. The oscillating signal source is configured to provide a reference signal having a reference frequency. The modulus compensator is coupled to the oscillating signal source and is configured to receive the reference signal. The modulus compensator is configured to produce a compensated modulus value based on the reference frequency, a fixed oscillator frequency of a fixed-frequency oscillator signal, and a modulus value. The frequency generator is coupled to the oscillating signal source and the modulus compensator and is configured to receive the compensated modulus value. The frequency generator is configured to generate an output signal having an output frequency that is based on the reference frequency and the compensated modulus value.Type: GrantFiled: September 14, 2018Date of Patent: April 7, 2020Assignee: QUALCOMM IncorporatedInventors: Kevin Jia-Nong Wang, Shyam Sivakumar
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Publication number: 20200106446Abstract: This disclosure provides a method and apparatus for a temperature-compensated oscillator. In some example implementations, the temperature-compensated oscillator may include a first oscillator, a second oscillator, and a temperature compensation block. The first oscillator may generate a first periodic clock signal and the second oscillator may generate a second periodic clock signal. The temperature-compensating block may generate a compensation signal based on the first period clock signal and the second periodic clock signal.Type: ApplicationFiled: June 25, 2019Publication date: April 2, 2020Inventors: Shyam SIVAKUMAR, Kevin Jia-Nong WANG, Anish CHIVUKULA
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Publication number: 20200091918Abstract: An apparatus is disclosed that implements frequency synthesis with accelerated locking. In an example aspect, the apparatus includes an oscillating signal source, a modulus compensator, and a frequency generator. The oscillating signal source is configured to provide a reference signal having a reference frequency. The modulus compensator is coupled to the oscillating signal source and is configured to receive the reference signal. The modulus compensator is configured to produce a compensated modulus value based on the reference frequency, a fixed oscillator frequency of a fixed-frequency oscillator signal, and a modulus value. The frequency generator is coupled to the oscillating signal source and the modulus compensator and is configured to receive the compensated modulus value. The frequency generator is configured to generate an output signal having an output frequency that is based on the reference frequency and the compensated modulus value.Type: ApplicationFiled: September 14, 2018Publication date: March 19, 2020Inventors: Kevin Jia-Nong Wang, Shyam Sivakumar
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Patent number: 10539470Abstract: A sub-threshold MOSFET temperature sensor is provided in which a sub-threshold leakage current through a sub-threshold transistor having its source connected to its gate is mirrored through a diode-connected transistor to produce an output voltage. Feedback maintains a drain voltage for the sub-threshold transistor to equal the output voltage.Type: GrantFiled: October 19, 2017Date of Patent: January 21, 2020Assignee: QUALCOMM IncorporatedInventor: Kevin Jia-Nong Wang
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Patent number: 10374651Abstract: An apparatus is disclosed for relocking of a locked loop. In an example aspect, the apparatus includes a locked loop, and the locked loop includes a loop and a locked-loop controller that is coupled to the loop. The loop is configured to run responsive to a run signal. The loop includes a memory state component and signal characteristic adjustment circuitry coupled to the memory state component. The signal characteristic adjustment circuitry is configured to produce an output signal having a characteristic that is based on the memory state component. The locked-loop controller is configured to receive an external power mode signal (EPMS). The locked-loop controller is also configured to generate the run signal to have an enable value at a first time when the EPMS is indicative of an external normal mode and at a second time when the EPMS is indicative of an external standby mode.Type: GrantFiled: September 29, 2018Date of Patent: August 6, 2019Assignee: QUALCOMM IncorporatedInventors: Shyam Sundar Sivakumar, Kevin Jia-Nong Wang
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Publication number: 20190120699Abstract: A sub-threshold MOSFET temperature sensor is provided in which a sub-threshold leakage current through a sub-threshold transistor having its source connected to its gate is mirrored through a diode-connected transistor to produce an output voltage. Feedback maintains a drain voltage for the sub-threshold transistor to equal the output voltage.Type: ApplicationFiled: October 19, 2017Publication date: April 25, 2019Inventor: Kevin Jia-Nong Wang
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Patent number: 10269490Abstract: A capacitor may include a first set of conductive fingers interdigitated with a second set of conductive fingers at an interconnect layer in a preferred direction of the interconnect layer. The capacitor may also include the first set of conductive fingers interdigitated with the second set of conductive fingers at a next interconnect layer in the preferred direction of the next interconnect layer. The capacitor may further include a first set of through finger vias electrically coupling the first set of conductive fingers of the interconnect layer to the first set of conductive fingers of the next interconnect layer.Type: GrantFiled: August 25, 2017Date of Patent: April 23, 2019Assignee: QUALCOMM IncorporatedInventors: Kevin Jia-Nong Wang, Chao Song
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Publication number: 20190015351Abstract: This disclosure relates to nanoparticles for preventing, treating and reversing atherosclerosis.Type: ApplicationFiled: July 13, 2018Publication date: January 17, 2019Inventors: Yinghui Zhong, Jia Nong, Zhicheng Wang
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Publication number: 20180315548Abstract: A capacitor may include a first set of conductive fingers interdigitated with a second set of conductive fingers at an interconnect layer in a preferred direction of the interconnect layer. The capacitor may also include the first set of conductive fingers interdigitated with the second set of conductive fingers at a next interconnect layer in the preferred direction of the next interconnect layer. The capacitor may further include a first set of through finger vias electrically coupling the first set of conductive fingers of the interconnect layer to the first set of conductive fingers of the next interconnect layer.Type: ApplicationFiled: August 25, 2017Publication date: November 1, 2018Inventors: Kevin Jia-Nong WANG, Chao SONG
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Patent number: 6697004Abstract: A novel mismatched-shaping DAC architecture is described. The inventive DAC partially spectrally shapes data conversion errors. In accordance with the present invention, the DAC mismatch-shaping function is fully effective for input signal amplitude levels that are relatively low (i.e., close to mid-scale), however, the mismatch-shaping function is not fully effective for input signal amplitude levels that are relatively high. This results in the simplification in complexity, reduced power dissipation, and shortened propagation delays associated with the mismatch-shaping DAC digital logic circuitry. Exemplary delta-sigma ADC and DAC architectures adapted for use with the present inventive partial mismatch-shaping DAC are also described.Type: GrantFiled: October 1, 2001Date of Patent: February 24, 2004Assignee: Silicon Wave, Inc.Inventors: Ian Andrew Galton, Jorge Alberto Grilo, Kevin Jia-Nong Wang