Abstract: Embodiments of the present application relate to a method for recommending target object information, a system for recommending target object information, a client for recommending target object information, a server for recommending target object information, and a computer program product for recommending target object information. A method for recommending target object information is provided. The method includes receiving a target object informational recommendation request including information pertaining to a plurality of short-listed objects selected, determining historical selection information on the plurality of short-listed objects, the historical selection information including a historical count, a selection count, or both, and sending the part or all of the short-listed object historical selection information to a client.

Abstract: A three-dimensional (3D) semiconductor device is provided, comprising a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer; and multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer in each of the sub-stacks.

Abstract: A 3D memory device includes a multi-layer stack, a first contact layer, a memory layer, a cannel layer. The multi-layer stack includes a plurality of conductive layers, a first opening and a second opening. The conductive layers are vertical stacked and insulated with each other. The first opening and the second opening respectively penetrate through at least two adjacent ones of the conductive layers. The first contact layer is disposed in the first opening and electrically connecting the conductive layers penetrated by the first opening. The memory layer is disposed in the second opening. The channel layer covers on the memory layer, wherein a plurality of memory cells are formed at cross points of the channel layer, the memory layer and the conductive layers penetrated by the second opening.

Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array region. The preliminary structure includes a plurality of first stacks in the array region. Then, a first dielectric layer is formed on the first stacks. A first hard mask layer is formed on the first dielectric layer. An insulating material is formed on the first hard mask layer. Then, a planarization process stopped on the first hard mask layer is conducted. Thereafter, the first hard mask layer is removed. A second hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the second hard mask layer. A plurality of contacts are formed through the second dielectric layer, the second hard mask layer and the first dielectric layer to the preliminary structure.

Abstract: Embodiments of the present application relate to a method for recommending target object information, a system for recommending target object information, a client for recommending target object information, a server for recommending target object information, and a computer program product for recommending target object information. A method for recommending target object information is provided. The method includes receiving a target object informational recommendation request including information pertaining to a plurality of short-listed objects selected, determining historical selection information on the plurality of short-listed objects, the historical selection information including a historical count, a selection count, or both, and sending the part or all of the short-listed object historical selection information to a client.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first stacked structures and two second stacked structures disposed on the substrate. Each of the first stacked structures includes alternately stacked metal layers and oxide layers. Each of the second stacked structures includes alternately stacked silicon nitride layers and oxide layers. The first stacked structures are disposed between the two second stacked structures.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.

Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.

Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.

Abstract: The present invention relates to a flat wall-mounted sun-tracking and light-guiding device with built-in sensors, which comprises a sun-tracking and light-guiding member, a sun-tracking controller, a light concentrator, and a switchable light emitter. The sun-tracking and light-guiding member owns the function of tracking the sun and is coupled to the sun-tracking controller. The light concentrator faces the sun and is used for concentrating the sunlight. In addition, the light concentrator is connected with the sun-tracking and light-guiding member. The light concentrator includes a light-guiding optical fiber, which is used for guiding the concentrated sunlight. Besides, the switchable light emitter is connected with one end of the light-guiding optical fiber. The switchable light emitter can be disposed indoors or on plant chambers for lighting the interior or plants using the sunlight guided by the light-guiding optical fiber.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

Abstract: The present invention provides a pipe straightener, which consists of three roller wheel units and a restraining sleeve, wherein each of the roller wheel units is juxtaposed, and the roller wheel units enclose and are configured to form a long straight-formed passageway. The passageway is used to enable metal pipes to pass therethrough. The restraining sleeve encloses and covers each of the roller wheel units, thereby restraining each of the roller wheel units. Each of the roller wheel units is mainly structured from a wheel carrier and a plurality of roller wheels. One side of the wheel carrier is a first side, and the other side is a second side. The first side is adjacent to the passageway, and the second side is adjacent to the restraining sleeve.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.

Abstract: A semiconductor device includes at least a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first stacked structures and two second stacked structures disposed on the substrate. Each of the first stacked structures includes alternately stacked metal layers and oxide layers. Each of the second stacked structures includes alternately stacked silicon nitride layers and oxide layers. The first stacked structures are disposed between the two second stacked structures.

Abstract: According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer.