Patents by Inventor Jia Rui
Jia Rui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966822Abstract: Disclosed are a computer-implemented method, a system and a computer program product for feature processing. In the computer-implemented method for feature processing, two input features selected from multiple features of each sample in a sample set are projected to one resulting feature by one or more processing units based on a specified curve. The sample set is updated by replacing the two input features with the one resulting feature for each sample in the sample set by one or more processing units. The projecting and the updating for the sample set are repeated by one or more processing units until the number of features of each sample in the sample set reaches a predetermined criterion.Type: GrantFiled: September 29, 2020Date of Patent: April 23, 2024Assignee: International Business Machines CorporationInventors: Chun Lei Xu, Si Er Han, Shi Bin Liu, Yi Shao, Lei Tian, Hao Zheng, Jia Rui Wang
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Patent number: 11894459Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.Type: GrantFiled: January 5, 2021Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chih Su, Ruey-Hsin Liu, Pei-Lun Wang, Jia-Rui Lee, Jyun-Guan Jhou
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Publication number: 20230404845Abstract: A foam stick includes a tube body, a core, and two covers. The tube body has an accommodating groove with two open ends. The core is disposed in the accommodating groove of the tube body. The two covers are disposed at both ends of the tube body to close the accommodating groove. The foam stick is composed of the tube body, the core and the covers, so the material utilization rate is high. Through the combination of the tube body, the core and the covers, the foam stick has different characteristics and can be used as rollers or floats.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Inventors: TIEN-SZU HSU, SHU-JIN CHEN, YI-PING CHUNG, JIA-RUI XU, GENG-LIN LIU, CHUNG-LUN CHAN
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Publication number: 20230405405Abstract: A balance pad includes a base. A plurality of first pillars and a peripheral wall are uprightly disposed on the base. The peripheral wall surrounds the first pillars so that the first pillars are located within the peripheral wall. Thereby, the first pillars reduce the stability of the balance pad to increase the difficulty of doing balance exercise. The peripheral wall surrounds the first pillars, so that the first pillars can abut against the peripheral wall to avoid excessive inclination of the first pillars to cause injury to a user.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Inventors: TIEN-SZU HSU, SHU-JIN CHEN, YI-PING CHUNG, JIA-RUI XU, GENG-LIN LIU, CHUNG-LUN CHAN
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Publication number: 20230335640Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.Type: ApplicationFiled: June 21, 2023Publication date: October 19, 2023Inventors: JIA-RUI LEE, KUO-MING WU, YI-CHUN LIN
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Publication number: 20230320104Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having two bottom electrodes and one top electrode. The present disclosure provides a structure including a first bottom electrode having an upper surface, a second bottom electrode having an upper surface, a switching layer on the upper surface of the first electrode and the upper surface of the second electrode, an oxygen enhancement layer on the switching layer, and a top electrode on the oxygen enhancement layer, the top electrode is positioned above the first bottom electrode and the second bottom electrode.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: JIA RUI THONG, JIANXUN SUN, ENG HUAT TOH, JUAN BOON TAN
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Patent number: 11721758Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.Type: GrantFiled: November 24, 2020Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jia-Rui Lee, Kuo-Ming Wu, Yi-Chun Lin
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Publication number: 20220384647Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chih SU, Ruey-Hsin LIU, Pei-Lun WANG, Jia-Rui LEE, Jyun-Guan JHOU
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Publication number: 20220309610Abstract: A method is provided and includes acquiring a digital slide comprising objects of at least two sizes, the objects including a first object of a first size and a second object of a second size different from the first size, for each of the first object and the second object, acquiring images of a corresponding object in at least two scales based on the digital slide, where the acquired images of the corresponding object in the at least two scales include an image of a larger scale and an image of a smaller scale, the image of the larger scale having a smaller image size and a higher image resolution than the image of the smaller scale, and determining, from the images of the corresponding object in the at least two scales, an image having an image size that corresponds to a size of the corresponding object.Type: ApplicationFiled: March 3, 2022Publication date: September 29, 2022Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Liang WANG, Jia Rui SUN, Yan Chun ZHU, Jianhua YAO
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Publication number: 20220158093Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides and a top surface, in which the sides taper towards each other as they meet the top surface, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top surface of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventors: JIA RUI THONG, JIANXUN SUN, YI JIANG, JUAN BOON TAN
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Publication number: 20220101183Abstract: Disclosed are a computer-implemented method, a system and a computer program product for feature processing. In the computer-implemented method for feature processing, two input features selected from multiple features of each sample in a sample set are projected to one resulting feature by one or more processing units based on a specified curve. The sample set is updated by replacing the two input features with the one resulting feature for each sample in the sample set by one or more processing units. The projecting and the updating for the sample set are repeated by one or more processing units until the number of features of each sample in the sample set reaches a predetermined criterion.Type: ApplicationFiled: September 29, 2020Publication date: March 31, 2022Inventors: Chun Lei Xu, Si Er Han, Shi Bin Liu, Yi Shao, Lei Tian, Hao Zheng, Jia Rui Wang
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Publication number: 20220029020Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.Type: ApplicationFiled: January 5, 2021Publication date: January 27, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chih SU, Ruey-Hsin LIU, Pei-Lun WANG, Jia-Rui LEE, Jyun-Guan JHOU
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Patent number: 11189613Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a transistor and a diode. The transistor includes a first gate region electrically coupled to a gate driver, and a first source region and a first drain region on two sides of the first gate region. The diode includes two terminals coupled between the first drain region of the transistor and a reference voltage. The transistor has a threshold voltage greater than that of the diode.Type: GrantFiled: December 10, 2019Date of Patent: November 30, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jia-Rui Lee, Kuo-Ming Wu, Yi-Chun Lin, Alexander Kalnitsky
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Publication number: 20210074854Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.Type: ApplicationFiled: November 24, 2020Publication date: March 11, 2021Inventors: JIA-RUI LEE, KUO-MING WU, YI-CHUN LIN
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Patent number: 10847650Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.Type: GrantFiled: October 23, 2019Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jia-Rui Lee, Kuo-Ming Wu, Yi-Chun Lin
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Publication number: 20200118997Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a transistor and a diode. The transistor includes a first gate region electrically coupled to a gate driver, and a first source region and a first drain region on two sides of the first gate region. The diode includes two terminals coupled between the first drain region of the transistor and a reference voltage. The transistor has a threshold voltage greater than that of the diode.Type: ApplicationFiled: December 10, 2019Publication date: April 16, 2020Inventors: JIA-RUI LEE, KUO-MING WU, YI-CHUN LIN, ALEXANDER KALNITSKY
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Publication number: 20200058789Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.Type: ApplicationFiled: October 23, 2019Publication date: February 20, 2020Inventors: JIA-RUI LEE, KUO-MING WU, YI-CHUN LIN
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Patent number: 10509631Abstract: Techniques for customizing a software product may include receiving customization information describing customizations to the software product requested by a user; submitting a request including the customization information to a web service; and responsive to receiving the request, performing processing comprising: creating, by the web service, a new job to generated a customized version of the software product in accordance with the customization information of the request; automatically generating at least one customized file in accordance with the customization information; generating the customized version of the software product including the at least one customized file; and testing the customized version of the software product.Type: GrantFiled: April 16, 2018Date of Patent: December 17, 2019Assignee: EMC IP Holding Company LLCInventors: Wei Duan, Qiang Ma, Jia Rui Tang
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Patent number: 10505038Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.Type: GrantFiled: September 28, 2017Date of Patent: December 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jia-Rui Lee, Kuo-Ming Wu, Yi-Chun Lin
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Patent number: D955390Type: GrantFiled: May 11, 2020Date of Patent: June 21, 2022Assignee: INTERMEC IP CORPORATIONInventors: Yinlei Zhang, Yijing Hou, Jia Rui Huang, Shuming Li, Tiecheng Qu, Zhao Xia Jin