Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region and a gate structure extending into the substrate, wherein a portion of the gate structure below a top surface of the substrate abuts the isolation region. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: A process for fabricating a semiconductor structure is disclosed. The process includes: forming an isolation trench in a substrate; forming a trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a portion in contact with the substrate below an upper surface of the substrate; exposing a sidewall of the isolation trench and without exposing a bottom of the isolation trench in the substrate; and forming a gate structure over the substrate, wherein the gate structure contacts the sidewall of the isolation trench.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

Abstract: A method is provided and includes acquiring a digital slide comprising objects of at least two sizes, the objects including a first object of a first size and a second object of a second size different from the first size, for each of the first object and the second object, acquiring images of a corresponding object in at least two scales based on the digital slide, where the acquired images of the corresponding object in the at least two scales include an image of a larger scale and an image of a smaller scale, the image of the larger scale having a smaller image size and a higher image resolution than the image of the smaller scale, and determining, from the images of the corresponding object in the at least two scales, an image having an image size that corresponds to a size of the corresponding object.

Abstract: Disclosed are a computer-implemented method, a system and a computer program product for feature processing. In the computer-implemented method for feature processing, two input features selected from multiple features of each sample in a sample set are projected to one resulting feature by one or more processing units based on a specified curve. The sample set is updated by replacing the two input features with the one resulting feature for each sample in the sample set by one or more processing units. The projecting and the updating for the sample set are repeated by one or more processing units until the number of features of each sample in the sample set reaches a predetermined criterion.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

Abstract: A foam stick includes a tube body, a core, and two covers. The tube body has an accommodating groove with two open ends. The core is disposed in the accommodating groove of the tube body. The two covers are disposed at both ends of the tube body to close the accommodating groove. The foam stick is composed of the tube body, the core and the covers, so the material utilization rate is high. Through the combination of the tube body, the core and the covers, the foam stick has different characteristics and can be used as rollers or floats.

Abstract: A balance pad includes a base. A plurality of first pillars and a peripheral wall are uprightly disposed on the base. The peripheral wall surrounds the first pillars so that the first pillars are located within the peripheral wall. Thereby, the first pillars reduce the stability of the balance pad to increase the difficulty of doing balance exercise. The peripheral wall surrounds the first pillars, so that the first pillars can abut against the peripheral wall to avoid excessive inclination of the first pillars to cause injury to a user.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having two bottom electrodes and one top electrode. The present disclosure provides a structure including a first bottom electrode having an upper surface, a second bottom electrode having an upper surface, a switching layer on the upper surface of the first electrode and the upper surface of the second electrode, an oxygen enhancement layer on the switching layer, and a top electrode on the oxygen enhancement layer, the top electrode is positioned above the first bottom electrode and the second bottom electrode.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

Abstract: A method is provided and includes acquiring a digital slide comprising objects of at least two sizes, the objects including a first object of a first size and a second object of a second size different from the first size, for each of the first object and the second object, acquiring images of a corresponding object in at least two scales based on the digital slide, where the acquired images of the corresponding object in the at least two scales include an image of a larger scale and an image of a smaller scale, the image of the larger scale having a smaller image size and a higher image resolution than the image of the smaller scale, and determining, from the images of the corresponding object in the at least two scales, an image having an image size that corresponds to a size of the corresponding object.

Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides and a top surface, in which the sides taper towards each other as they meet the top surface, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top surface of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.

Abstract: Disclosed are a computer-implemented method, a system and a computer program product for feature processing. In the computer-implemented method for feature processing, two input features selected from multiple features of each sample in a sample set are projected to one resulting feature by one or more processing units based on a specified curve. The sample set is updated by replacing the two input features with the one resulting feature for each sample in the sample set by one or more processing units. The projecting and the updating for the sample set are repeated by one or more processing units until the number of features of each sample in the sample set reaches a predetermined criterion.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a transistor and a diode. The transistor includes a first gate region electrically coupled to a gate driver, and a first source region and a first drain region on two sides of the first gate region. The diode includes two terminals coupled between the first drain region of the transistor and a reference voltage. The transistor has a threshold voltage greater than that of the diode.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.