Patents by Inventor Jia T. Wang

Jia T. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200303250
    Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 24, 2020
    Inventors: Xi CEN, Feiyue MA, Kai WU, Yu LEI, Kazuya DAITO, Yi XU, Vikash BANTHIA, Mei CHANG, He REN, Raymond Hoiman HUNG, Yakuan YAO, Avgerinos V. GELATOS, David T. OR, Jing ZHOU, Guoqiang JIAN, Chi-Chou LIN, Yiming LAI, Jia YE, Jenn-Yue WANG
  • Patent number: 4512815
    Abstract: In a monolithic semiconductor integrated circuit, conventional bipolar transistors are fabricated along with thin ion implanted junction field effect transistors, to create BIFET structures. After the conventional isolation diffusion, the surface oxide is stripped off and the semiconductor wafer ion implanted with slow diffusing impurities of a conductivity type, the same as the undiffused surface material. Then the bipolar transistors, along with the junction field effect transistors, are fabricated using conventional oxide masked diffusion processes. The field effect device sources and drains employ the base diffusions of the bipolar transistors while the gate contact is achieved with an emitter diffusion. The field effect device channels are formed at a depth substantially greater than that of the impurities deposited in the original ion implant. If desired, an ion implanted top gate can be established over the channel. The wafer is then annealed and processed in accordance with conventional techniques.
    Type: Grant
    Filed: January 31, 1983
    Date of Patent: April 23, 1985
    Assignee: National Semiconductor Corporation
    Inventors: Wadie N. Khadder, Jia T. Wang, Brian E. Hollins
  • Patent number: 4412238
    Abstract: In a monolithic semiconductor integrated circuit, conventional bipolar transistors are fabricated along with thin ion implanted junction field effect transistors, to create BIFET structures. After the conventional isolation diffusion, the surface oxide is stripped off and the semiconductor wafer ion implanted with slow diffusing impurities of a conductivity type, the same as the undiffused surface material. Then the bipolar transistors, along with the junction field effect transistors, are fabricated using conventional oxide masked diffusion processes. The field effect device sources and drains employ the base diffusions of the bipolar transistors while the gate contact is achieved with an emitter diffusion. The field effect device channels are formed at a depth substantially greater than that of the impurities deposited in the original ion implant. If desired, an ion implanted top gate can be established over the channel. The wafer is then annealed and processed in accordance with conventional techniques.
    Type: Grant
    Filed: May 27, 1980
    Date of Patent: October 25, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Wadie N. Khadder, Jia T. Wang, Brian E. Hollins