Abstract: A method is provided for use with an integrated circuit which includes a npn bipolar transistor on which a variable thickness oxide layer has been formed, the method for improving the radiation hardness of the transistor comprising the steps of: removing the variable thickness oxide layer; and forming a new oxide layer on the transistor, the new oxide layer having less overall volume than the removed variable thickness oxide layer.

Abstract: The surface area of a junction-isolated tub in a silicon epitaxial layer grown on a silicon substrate is increased by introducing dopant into surface portions of the tub to effectively push back the junction between the tub and the isolation region. The junction-isolation region surrounding the tub typically has a dopant concentration profile which decreases from the center of the junction-isolation region towards the junction with the tub. By increasing the surface concentration of dopant in the tube, the net dopant concentration of peripheral portions of the junction-isolation region is converted, thereby effectively increasing the size of the surface of the tub. The dopant concentration in the surface of the entire tub can be increased, or only the periphery of the tub can have increased dopant concentration, thereby maintaining the breakdown voltage of devices fabricated in the tub.

Abstract: The surface area of a junction-isolated tub in a silicon epitaxial layer grown on a silicon substrate is increased by introducing dopant into surface portions of the tub to effectively push back the junction between the tub and the isolation region. The junction-isolation region surrounding the tub typically has a dopant concentration profile which decreases from the center of the junction-isolation region towards the junction with the tub. By increasing the surface concentration of dopant in the tub, the net dopant concentration of peripheral portions of the junction-isolation region is converted, thereby effectively increasing the size of the surface of the tub. The dopant concentration in the surface of the entire tub can be increased, or only the periphery of the tub can have increased dopant concentration, thereby maintaining the breakdown voltage of devices fabricated in the tub.

Abstract: A process for doping a semiconductor material is performed during a deposition phase in a plurality of steps, first at a relatively low temperature to form a high concentration glass formation layer of the dopant on a semiconductor wafer at a high rate, and then raising the temperature slowly to provide an initial drive-in of the dopant. After etch removal of excess glass formation, the wafers are subjected to a base diffusion at an elevated temperature in an oxidizing atmosphere.

Abstract: A process for fabricating JFET devices into a conventional CMOS monolithic IC. The combination of devices provides linear circuit operation with low noise characteristics.