Patents by Inventor Jia-Wei Lin

Jia-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11002719
    Abstract: An actuating and sensing module includes a first substrate, a second substrate, an actuating device and a sensor. A gas flow channel is formed by stacking the first substrate and the second substrate. The gas inlet, the gas flow channel and the gas outlet are in communication with each other to define a gas flow loop. The actuating device is disposed in the gas inlet of the second substrate and electrically connected to a control circuit to obtain a driving power. The sensor is disposed in the gas flow loop and electrically connected to a control circuit of the first substrate to transmit sensed data. While the actuating device drives outside gas from the outside, the gas is transported into the gas flow loop and sensed by the sensor.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 11, 2021
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Li-Pang Mo, Jia-Yu Liao, Hung-Hsin Liao, Chih-Feng Lin, Jheng-Wei Chen, Chi-Feng Huang, Yung-Lung Han
  • Publication number: 20200271436
    Abstract: Provided herein are devices and systems comprising an illumination module configured to provide a source light to an optical interference module, which converts the source light to a line of light and processes light signal; an interference objective module, which handles light from the optical interference module and processes light signal generated from a sample; a two-dimensional camera configured to receive a backscattered interference signal from the sample, and a data processing module which processes the interference signal into an image.
    Type: Application
    Filed: September 18, 2018
    Publication date: August 27, 2020
    Inventors: Tuan-Shu HO, I-Ling CHEN, Dan JI, Sung Wei LU, Tzu Wei LIU, Jen Yu TSENG, Ting Yueh LIN, Chih Wei LU, Jia-Wei LIN, Yo Cheng CHUANG, Sheng-Lung HUANG
  • Patent number: 10477705
    Abstract: A storage device includes a first housing, a second housing, a circuit board, a first electric connector, a first storage unit, a second electric connector and a second storage unit. The second housing is matched with the first housing and connected with the first housing. The circuit board is disposed between the first housing and the second housing. The first electric connector is disposed on the circuit board. The first storage unit is disposed on the circuit board and electrically connected with the first electric connector. The second electric connector is disposed on the circuit board. The second storage unit is disposed on the circuit board and electrically connected with the second electric connector. The first storage unit and the second storage unit are independent from each other. Therefore, the advantages of utilizing two independent storage units on single one product are achieved.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: November 12, 2019
    Assignee: APACER TECHNOLOGY INC.
    Inventors: Jiunn-Chang Lee, Jia-Wei Lin, Liang-Cheng Li
  • Publication number: 20190124395
    Abstract: An image processing apparatus includes a frame buffer, a compression circuit, a prediction circuit and a memory management circuit. The frame buffer is configured to include multiple large pages and multiple small pages. The compression circuit compresses image data to generate compressed image data. The prediction circuit generates a predicted data size for the compressed image data. In response to a storage request of storing the compressed image data into the frame buffer, the memory management circuit allocates N number of large pages and M number of small pages to the compressed image data. According to the predicted data size, the memory management circuit determines an order of using the N number of large pages and the M number of small pages when the compressed image data is stored into the frame buffer.
    Type: Application
    Filed: January 18, 2018
    Publication date: April 25, 2019
    Inventor: Jia-Wei LIN
  • Patent number: 10025648
    Abstract: In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of hardware resources. Each virtual set of hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 17, 2018
    Assignee: Advantest Corporation
    Inventors: Klaus-Dieter Hilliges, Jia-Wei Lin, Duncan Gurley, Xiaomin Jin, Erik Volkerink
  • Publication number: 20170153830
    Abstract: A data storage device includes a volatile first storage unit, a non-volatile second storage unit and a control unit. The first storage unit is used for temporarily storing at least one data. The second storage unit includes plural backup spaces. A size of each backup space is larger than or equal to a size of the first storage unit. The control unit is electrically connected with the first storage unit and the second storage unit. The control unit accesses the at least one data according to a control command, and the control unit periodically writes the at least one data to one of the plural backup spaces.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 1, 2017
    Inventors: Jiunn-Chang Lee, Jia-Wei Lin
  • Patent number: 9483415
    Abstract: An apparatus for managing a memory including a working region and a compression region is provided. The working region stores uncompressed data. The apparatus includes a management module and a compression/decompression module. According to a recent used index and a compression ratio of a set of target data stored in the working region, the management module determines whether to transfer the target data to the compression region. When the management module determines to transfer the target data to the compression region, the compression/decompression module compresses the target data and transfers the compressed target data to the compression region.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 1, 2016
    Assignee: MStar Semiconductor, Inc.
    Inventors: Yi-Shin Tung, He-Yuan Lin, Jia-Wei Lin, Hung-Wei Yang
  • Publication number: 20160179833
    Abstract: A related information display method includes following steps. In step (a), a maximum word count of consecutive same words between a candidate text paragraph and a target text string to determine a similarity level. In step (b), it is determined whether to display related information of the target text string according to the similarity level. The related information is a website link associated with the target text string. The candidate text string may be dialogues in a communication software interface, text on a webpage, or text of a document in an electronic device. The target text string may be a name of a television program, a name of a place, a name of a movie, a name of a song, a name of a person, or a name of an object.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 23, 2016
    Inventor: Jia-Wei LIN
  • Patent number: 9317351
    Abstract: In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 19, 2016
    Assignee: ADVANTEST CORPORATION
    Inventors: Klaus-Dieter Hilliges, Jia-Wei Lin, Duncan Gurley, Jim-my Jin, Eric Vokerink
  • Publication number: 20150370248
    Abstract: In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of hardware resources. Each virtual set of hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Applicant: ADVANTEST CORPORATION
    Inventors: Klaus-Dieter Hilliges, Jia-Wei Lin, Duncan Gurley, Jim-my Jin, Eric Volkerink
  • Publication number: 20150089170
    Abstract: An apparatus for managing a memory including a working region and a compression region is provided. The working region stores uncompressed data. The apparatus includes a management module and a compression/decompression module. According to a recent used index and a compression ratio of a set of target data stored in the working region, the management module determines whether to transfer the target data to the compression region. When the management module determines to transfer the target data to the compression region, the compression/decompression module compresses the target data and transfers the compressed target data to the compression region.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 26, 2015
    Inventors: Yi-Shin Tung, He-Yuan Lin, Jia-Wei Lin, Hung-Wei Yang
  • Publication number: 20140189430
    Abstract: In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.
    Type: Application
    Filed: September 7, 2010
    Publication date: July 3, 2014
    Applicant: VERIGY (SINGAPORE) PTE. LTD.
    Inventors: Klaus-Dieter Hilliges, Jia-Wei Lin, Duncan Gurley, Jimmy Xiaomin Jin, Erik H. Volkerink