Patents by Inventor Jia-Wei Yang

Jia-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040171220
    Abstract: A fabrication method for a semiconductor device. On a semiconductor silicon substrate with a first type conductivity, an epitaxial layer with a second type conductivity and an oxide layer on the epitaxial layer are formed with at least a deep trench. Ion implantation is used to form an ion diffusion region with the first type conductivity which is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An oxide liner is formed on the sidewall and bottom of the deep trench, and then an undoped polysilicon layer is formed to fill the deep trench. The combination of the ion diffusion region and the undoped polysilicon layer serves as a deep trench isolation structure.
    Type: Application
    Filed: March 8, 2004
    Publication date: September 2, 2004
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jia-Wei Yang, Chih-Cherng Liao
  • Publication number: 20040082140
    Abstract: A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffusion region with the first type conductivity is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An undoped polysilicon layer fills the deep trench.
    Type: Application
    Filed: January 30, 2003
    Publication date: April 29, 2004
    Inventors: Jia-Wei Yang, Chih-Cherng Liao
  • Patent number: 6680231
    Abstract: A high-voltage device process compatible with a low-voltage device process. A high-voltage device area and a low-voltage device area are defined on an epitaxial layer of a semiconductor substrate. After forming a plurality of first gate structures on the high-voltage device area, a P-body is formed in the epitaxial layer between two adjacent first gate structures. Then, a plurality of second gate structures is formed on the low-voltage device area.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: January 20, 2004
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jia-Wei Yang, Chih-Cherng Liao