Patents by Inventor Jia Yi Wong

Jia Yi Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11217529
    Abstract: A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies AG
    Inventors: Stefan Beyer, Marius Aurel Bodea, Jia Yi Wong
  • Publication number: 20210305198
    Abstract: A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 30, 2021
    Inventors: Carsten von Koblinski, Daniel Pedone, Matteo Piccin, Roland Rupp, Chiew Li Tai, Jia Yi Wong
  • Patent number: 11107754
    Abstract: An electronic device and method is disclosed. In one example, the electronic device includes a semiconductor chip and a leadframe. The leadframe includes a first class of leads and a second class of leads. The leads of the second class of leads are thinner than leads of the first class of leads.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: August 31, 2021
    Assignee: Infineon Technologies AG
    Inventors: Jia Yi Wong, Kar Meng Ho
  • Publication number: 20210043549
    Abstract: A clip for a semiconductor package includes a first portion and a second portion. The first portion includes a first surface, a second surface opposite to the first surface and configured to contact a first electrically conductive component, and a stepped region between the first surface and the second surface such that the second surface has a smaller area than the first surface. The second portion is coupled to the first portion and configured to contact a second electrically conductive component. The second portion includes a third surface aligned with the first surface.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 11, 2021
    Applicant: Infineon Technologies AG
    Inventors: Ke Yan Tean, Mei Fen Hiew, Jia Yi Wong
  • Patent number: 10727151
    Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies AG
    Inventors: Liu Chen, Teck Sim Lee, Jia Yi Wong, Wei Han Koo, Thomas Stoeck, Gilles Delarozee
  • Publication number: 20200111750
    Abstract: A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 9, 2020
    Applicant: Infineon Technologies AG
    Inventors: Stefan Beyer, Marius Aurel Bodea, Jia Yi Wong
  • Patent number: 10431526
    Abstract: A metal heat slug having an upper and lower surface is provided. First and second electrically conductive leads are provided. First and second electrically insulating fastening mechanisms are provided. The first and second fastening mechanisms are adhered to the upper surface of the heat slug in an outer peripheral region of the heat slug such that the first and second leads are vertically separated from and electrically insulated from the heat slug. The central die attach region is exposed from the first and second fastening mechanisms after adhering the first and second fastening mechanisms to the upper surface of the heat slug.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 1, 2019
    Assignee: Cree, Inc.
    Inventors: Kar Meng Ho, Chiew Li Tai, Jia Yi Wong, Sanjay Kumar Murugan
  • Publication number: 20190109070
    Abstract: A metal heat slug having an upper and lower surface is provided. First and second electrically conductive leads are provided. First and second electrically insulating fastening mechanisms are provided. The first and second fastening mechanisms are adhered to the upper surface of the heat slug in an outer peripheral region of the heat slug such that the first and second leads are vertically separated from and electrically insulated from the heat slug. The central die attach region is exposed from the first and second fastening mechanisms after adhering the first and second fastening mechanisms to the upper surface of the heat slug.
    Type: Application
    Filed: October 9, 2017
    Publication date: April 11, 2019
    Inventors: Kar Meng Ho, Chiew Li Tai, Jia Yi Wong, Sanjay Kumar Murugan
  • Publication number: 20180358287
    Abstract: An electronic device and method is disclosed. In one example, the electronic device includes a semiconductor chip and a leadframe. The leadframe includes a first class of leads and a second class of leads. The leads of the second class of leads are thinner than leads of the first class of leads.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 13, 2018
    Applicant: Infineon Technologies AG
    Inventors: Jia Yi Wong, Kar Meng Ho
  • Publication number: 20180342438
    Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventors: Liu Chen, Teck Sim Lee, Jia Yi Wong, Wei Han Koo, Thomas Stoek, Gilles Delarozee
  • Patent number: 8877617
    Abstract: A method for forming of a thin film on a substrate is disclosed. The method includes cleaning a process chamber by flowing a first gas having fluorine. The method also includes coating the process chamber with a first encapsulating layer including amorphous silicon (A-Si) by flowing a second gas for a first duration, where the first encapsulating layer protects against fluorine contamination. The method further includes loading a substrate into the process chamber, depositing a thin film on the substrate by flowing a third gas into the process chamber and unloading the substrate from the process chamber. The thin film can include silicon nitride (SiN), the first gas can include nitrogen triflouride (NF3) gas and second gas can include silane (SiH4) gas. The thin film can be formed using plasma-enhanced chemical vapor deposition. The substrate can be a solar cell or a liquid crystal display (LCD).
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 4, 2014
    Assignee: SunPower Corporation
    Inventors: Jia Yi Wong, Thomas Qiu