Patents by Inventor Jia An Huang

Jia An Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240196074
    Abstract: This disclosure provides a lens assembly that has an optical path and includes a lens element and a light-blocking membrane layer. The lens element has an optical portion, and the optical path passes through the optical portion. The light-blocking membrane layer is coated on the lens element and adjacent to the optical portion. The light-blocking membrane layer has a distal side and a proximal side that is located closer to the optical portion than the distal side. The proximal side includes two extension structures and a recessed structure. Each of the extension structures extends along a direction away from the distal side, and the extension structures are not overlapped with each other in a direction in parallel with the optical path. The recessed structure is connected to the extension structures and recessed along a direction towards the distal side.
    Type: Application
    Filed: January 26, 2024
    Publication date: June 13, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Jyun-Jia CHENG, Yu Chen LAI, Ming-Ta CHOU, Cheng-Feng LIN, Chen-Yi HUANG
  • Patent number: 12010933
    Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
  • Patent number: 12008567
    Abstract: Methods and systems are presented for analyzing transactions conducted through user accounts with an online service provider based on graph analysis. A graph is generated based on a set of seed accounts that are determined to be involved in suspicious activities. The graph includes a set of seed nodes representing the seed accounts, and a set of nodes representing user accounts that are connected to the set of seed accounts in downstream transactions. A random walk traversal based on multiple dimensions is performed on the graph to determine nodes that are closely related to the set of seed nodes. Transactions conducted through the seed accounts and accounts corresponding to nodes that are closely related to the set of seed nodes are analyzed to detect any malicious activities. The graph may also be presented according to a layered hierarchical structure for better visualization of transaction flows through the accounts.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: June 11, 2024
    Assignee: PayPal, Inc.
    Inventors: Jia Shi, Lin Zhu, Jie Huang
  • Publication number: 20240174826
    Abstract: The present disclosure provides an ionic gel film preparation method, a chemical sensor and preparation method thereof, relating to the field of sensor technology. The preparation method of ionic gel film includes: blending a vinyl-free ionic liquid with a vinyl-containing ionic liquid and a specified additive to obtain a homogenous solution, taking a predetermined amount of the homogenous solution and dropping it onto a first substrate equipped with interdigital electrodes, flattening the homogenous solution on the first substrate using a second substrate, curing the flattened homogenous solution on the first substrate using ultraviolet light of a preset wavelength, and curing until the vinyl-containing ionic liquid polymerizes in situ to form an ionic gel film. The preparation method of ionic gel film, chemical sensor, and preparation method thereof of the present disclosure have the advantages of good device consistency, high conductivity, and good sensing performance when using the ionic gel film.
    Type: Application
    Filed: November 23, 2023
    Publication date: May 30, 2024
    Applicant: Tongji University
    Inventors: Jia HUANG, Li LI, Tongrui SUN
  • Patent number: 11995390
    Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Jerry Chang Jui Kao, Pin-Dai Sue, Jiun-Jia Huang, Yu-Ti Su, Wei-Hsiang Ma
  • Patent number: 11994536
    Abstract: The present invention provides a system for data mapping and storing in digital three-dimensional oscilloscope, wherein the fixed coefficients, which are calculated according the parameters and settings of a digital oscilloscope, are stored into a fixed coefficient memory CO RAM, the fixed coefficients are outputted to N fractional operation units through N?1 D flip-flop delay units to multiply with the acquired data x(n) and then be accumulated, thus N fractional calculus results are obtained. In this way, N fractional calculus results can be obtained by performing L/N fractional calculus operations. N fractional calculus results are sent to a signal processing and display module, in which they are converted into a display data through a drawing thread, and the display data are sent to LCD for displaying, thus the fractional calculus operation and display of a input signal in a digital oscilloscope is realized.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: May 28, 2024
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Bo Xu, Kai Chen, Libing Bai, Lulu Tian, Hang Geng, Yuhua Cheng, Songting Zou, Jia Zhao, Yanjun Yan, Xiaoyu Huang
  • Publication number: 20240161343
    Abstract: An image processing method includes following operations: receiving, by a processor, an input image from a camera; performing, by the processor, a top-view calibration process to generate a top-view calibrated image according to the input image; performing, by the processor, an object extraction process on the top-view calibrated image to generate at least one target object frame; performing, by the processer, a centering process on the at least one target object frame to generate a centered image; and outputting, by the processor, the centered image for a display panel to display.
    Type: Application
    Filed: June 7, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Hsuan HUANG, Yao-Jia KUO, Yu-Chi TSAI, Wen-Tsung HUANG
  • Publication number: 20240141532
    Abstract: A negative electrode composite current collector including a copper plating solution is described. The copper plating solution includes a leveling agent represented by a general formula (1) where an anion X is F?, Cl?, or Br?; R1, R2, and R3 are each independently selected from O or S; and R4, R5, and R6 are each independently selected from hydrogen, a substituted or unsubstituted alkyl, a substituted or unsubstituted vinyl, a substituted or unsubstituted aryl, and a substituted or unsubstituted heteroaryl.
    Type: Application
    Filed: December 14, 2023
    Publication date: May 2, 2024
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Jia PENG, Mingling LI, Xin LIU, Qisen HUANG
  • Publication number: 20240138049
    Abstract: A power supply device having a thermal insulation function includes a circuit board, and at least one heat-sensitive component and a plurality of heat-generating electronic components that are disposed on the circuit board and spaced apart from one another. The heat-generating electronic components include a transformer, an inductor, an integrated circuit, or a metal oxide semiconductor (MOS). A minimum distance between the heat-sensitive component and the heat-generating electronic components is 7 mm. A thermal insulation area is defined between the heat-sensitive component and the heat-generating electronic components, and none of the heat-generating electronic components is disposed within a 270° range of the thermal insulation area. The heat-generating electronic components are disposed outside the thermal insulation area to separate the heat-sensitive component from a heat source on the circuit board, such that a high temperature of the heat source has less influence on the heat-sensitive component.
    Type: Application
    Filed: May 6, 2023
    Publication date: April 25, 2024
    Inventors: JERRYSON LEE, Ethan Lee, Yu-Jia Huang, KUO-SUNG HUANG
  • Publication number: 20240138087
    Abstract: A power conversion device having a temperature determination function is provided. The power conversion device is disposed on a light fixture and includes a housing, a power converter, and at least one temperature determination component. The power converter and the temperature determination component are disposed within the housing, and the temperature determination component is a temperature fuse. When an ambient temperature of the power converter reaches a preset temperature, the temperature determination component melts to indicate that the power converter is used under the abnormal ambient temperature. Accordingly, the ambient temperature of the power converter can be determined to be abnormal.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 25, 2024
    Inventors: JERRYSON LEE, Ethan Lee, Yu-Jia Huang, KUO-SUNG HUANG
  • Patent number: 11966424
    Abstract: Embodiments of this application disclose a method and for dividing geographical regions performed by a computing device. The method includes: encoding latitudes and longitudes in a first dataset to obtain a second dataset, the first dataset recording N groups of latitudes and longitudes, and the second dataset recording N region numbers, and each of the region numbers being used for representing a corresponding geographical region; obtaining a third dataset from the second dataset, the third dataset recording M groups of the region numbers, corresponding central point latitudes and central point longitudes in the geographical regions represented by the region numbers; and dividing the geographical regions represented by the M groups of region numbers into P regions according to the third dataset, each of the regions including at least one of the geographical regions represented by the corresponding group of region numbers.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 23, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Fei Huang, Fan Yang, Yanchun Lin, Jia Liu, Rui Guo
  • Patent number: 11967675
    Abstract: The present invention generally relates to electrolytes for use in various electrochemical devices. In some cases, the electrolytes are relatively safe to use; for example, the electrolytes may be resistant to overheating, catching on fire, burning, exploding, etc. In some embodiments, such electrolytes may be useful for certain types of high-voltage cathode materials. In some cases, the electrolytes may include ion dissociation compounds that can dissociate tight ion pairs. Non-limiting examples of ion dissociation compounds include trialkyl phosphates, sulfones, or the like. Other aspects of the invention are generally directed to devices including such electrolytes, methods of making or using such electrolytes, kits including such electrolytes, or the like.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Factorial Inc.
    Inventors: Jia Du, Peishen Huang, Karlie Mellott, Dong Ren
  • Publication number: 20240117335
    Abstract: Provided are fusion proteins that include an apolipoprotein B mRNA editing enzyme catalytic subunit 3A (APOBEC3A) and a clustered regularly interspaced short palindromic repeats (CRISPR)-associated (Cas) protein, optionally further with uracil glycosylase inhibitor (UGI). Such a fusion protein is able to conduct base editing in DNA by deaminating cytosine to uracil, even when the cytosine is in a GpC context or is methylated.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 11, 2024
    Inventors: Jia CHEN, Li Yang, Xingxu Huang, Bei Yang, Xiao Wang, Jianan Li
  • Patent number: 11956938
    Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Kuan-Lun Cheng, Yasutoshi Okuno, Jiun-Jia Huang
  • Publication number: 20240109947
    Abstract: Novel cytokine combinations comprising the combination of a type I cytokine, e.g., interleukin-2 (IL-2), or an IL-2 superkine variant (super-2); and a type II cytokine, e.g., IL-33 or IL-25 are provided for use in treating cancer or infection, e.g., solid tumors. These cytokines may be administered in soluble form or may be expressed by cells, e.g., immune cells which express an endogenous or chimeric receptor which binds to target cells, e.g., cancer cells such as those in a solid tumor.
    Type: Application
    Filed: July 26, 2023
    Publication date: April 4, 2024
    Inventors: Yina HUANG, Rachel BROG, Prathna KUMAR, Jia ZOU
  • Publication number: 20240113288
    Abstract: This application relates to a negative electrode plate, a secondary battery and apparatus thereof. The secondary battery of the present application comprises a negative electrode plate, the negative electrode plate comprises a composite current collector and a negative electrode active material layer disposed on at least one surface of the composite current collector, the negative electrode active material layer comprises a silicon-based active material, the silicon-based active material accounts for 0.5 wt % to 50 wt % of total mass of the negative electrode active material layer, and the composite current collector comprises a polymer support layer and a metal conductive layer disposed on at least one surface of the polymer support layer. The secondary battery and the negative electrode plate achieve good coordination between the current collector and the negative electrode active material layer.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 4, 2024
    Applicant: Contemporary Amperex Technology Co., Limited
    Inventors: Cheng LI, Qisen HUANG, Xin LIU, Changliang SHENG, Shiwen WANG, Xianghui LIU, Jia PENG, Mingling LI, Chengdu LIANG
  • Publication number: 20240108989
    Abstract: A game server generates a parallel-reality game that users may interact with in the real-world. The game server receives user information as users interact with game content. The game server includes a content marketplace that manages the exchange value of additional content items. The content marketplace matches additional game content with users playing the game based on the exchange value of the additional content items and user information. To do so, the content marketplace determines a propensity score for each additional content item quantifying a likelihood the user will interact with the additional content item while interacting with content in the parallel-reality game. The content marketplace provides the additional content item to the user's client device for display in the parallel-reality game based on the propensity score.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Piaw Na, Jia Huang, Hang Tan, Steve Zelinka, Herbert Law
  • Publication number: 20240113119
    Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Jiun-Jia Huang, Kuan-Lun Cheng, Chi-Hsing Hsu
  • Publication number: 20240107757
    Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Inventors: Jia He, Haihui Huang, Fandong Liu, Yaohua Yang, Peizhen Hong, Zhiliang Xia, Zongliang Huo, Yaobin Feng, Baoyou Chen, Qingchen Cao
  • Publication number: 20240104000
    Abstract: Determination and provision of improved representations of program flow control are provided by a method that monitors execution of binary code of a program on a computer system. The monitoring includes monitoring manipulation(s) of call stack(s) maintained by the computer system for the execution of the binary code. The method, based on the monitoring, determines function call pattern(s) and branch pattern(s) exhibited by the execution of the binary code. The method identifies, from the binary code and using the determined function call pattern(s) and branch pattern(s), function calls and branches, relations between the function calls and branches, and function and variable names. The method also provides a representation of program flow control of the program using the identified function calls and branches, relations, and function and variable names.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Bao Zhang, Jin Hong Fu, Peng Hui Jiang, Shi Chong Ma, He Huang, Jia Yu