Abstract: Disclosed are a negative electrode material, and a negative electrode plate and a battery including the negative electrode material. The negative electrode material includes a silicon material and a carbon material. The silicon material is distributed on a surface and in a pore of the carbon material, to form a silicon-carbon composite material that serves as a core. A surface of the silicon-carbon composite material is coated with a thin protective layer as a shell layer. The carbon material in the negative electrode material has a relatively large quantity of pores that may accommodate the silicon material and provide buffer space for volume expansion of the silicon material. In this way, the battery has a low cycling volume expansion rate.

Abstract: Disclosed are a negative electrode plate and a lithium-ion battery including the negative electrode plate. The negative electrode plate includes a negative electrode current collector and a negative electrode active material layer, the negative electrode active material layer is disposed on at least one surface of the negative electrode current collector, the negative electrode active material layer includes silicon-based material particles, and the silicon-based material particles include silicon oxide and/or silicon carbide; and the silicon-based material particles meet the following relationship: Di?35 ?m (I), di?25 ?m (II), 0.45?(?Ej2)/(?Di2)?0.75 (III), and (?Fk2)/(?Di2)?0.37 (IV), and a mixing amount of the silicon-based material particles meets the following relationship: 0.05?(?Fk2)/S?0.47 (V). The lithium-ion battery disclosed in the present disclosure has characteristics of high energy density and a long cycle life.

Abstract: Disclosed are a homogeneous silicon carbide material and an electrode plate and a battery that include the homogeneous silicon carbide material. A negative electrode plate in the battery of the present disclosure includes a homogeneous silicon carbide material. The homogeneous silicon carbide material includes an element Si and an element C. The homogeneous silicon carbide material is a homogeneous material and has a bi-continuous phase structure. The homogeneous silicon carbide material in the present disclosure has better cycling performance and higher specific capacity.

Abstract: A receiver-directed congestion control system which provides receiver-directed apportioning by adding a bandwidth share indicator value to the acknowledgement messages sent by the receiver to the senders. In certain embodiments, bandwidth share indicator value comprises the number of senders seen by the receiver. In other embodiments, the bandwidth share indicator value may comprise a percentage bandwidth share allocated to the sender computer to allow for varying priorities between senders. In the acknowledgement message, each sender may also include the incast degree, which is programmed in the application, to the receiver. This strategy enables the receiver to send back the sender count to all the senders as soon the first sender's packets arrive, even before the rest of the senders' packets arrive. Thus, the sender count and the incast degree look-ahead enable the receiver-directed system to achieve accurate and faster convergence of sending rates, without any repeated adjustments.

Abstract: A remote indirect memory access system and method for networked computer servers. The system comprises a network interface card having a network interface memory and a system memory operatively connected to the network interface card. The system memory has a plurality of electronic memory queues, wherein each of the memory queues corresponds to one of a plurality of receive processes in the computer server, with each of the memory queues having a corresponding head pointer and tail pointer. Each of the memory queues is assigned to receive electronic messages from a plurality of sender computers. The NIC comprises a tail pointer table, with the tail pointer table comprising initial memory location data of the tail pointers for the memory queues. The memory location data referenced by corresponding queue identifiers.

Abstract: A remote indirect memory access system and method for networked computer servers. The system comprises a network interface card having a network interface memory and a system memory operatively connected to the network interface card. The system memory has a plurality of electronic memory queues, wherein each of the memory queues corresponds to one of a plurality of receive processes in the computer server, with each of the memory queues having a corresponding head pointer and tail pointer. Each of the memory queues is assigned to receive electronic messages from a plurality of sender computers. The NIC comprises a tail pointer table, with the tail pointer table comprising initial memory location data of the tail pointers for the memory queues. The memory location data referenced by corresponding queue identifiers.

Abstract: A receiver-directed congestion control system which provides receiver-directed apportioning by adding a bandwidth share indicator value to the acknowledgement messages sent by the receiver to the senders. In certain embodiments, bandwidth share indicator value comprises the number of senders seen by the receiver. In other embodiments, the bandwidth share indicator value may comprise a percentage bandwidth share allocated to the sender computer to allow for varying priorities between senders. In the acknowledgement message, each sender may also include the incast degree, which is programmed in the application, to the receiver. This strategy enables the receiver to send back the sender count to all the senders as soon the first sender's packets arrive, even before the rest of the senders' packets arrive. Thus, the sender count and the incast degree look-ahead enable the receiver-directed system to achieve accurate and faster convergence of sending rates, without any repeated adjustments.

Abstract: A method of balancing load on multiple cores includes maintaining multiple bitmaps in a global memory location. Each bitmap indicates loads of the threads included in a thread domain. The multiple threads are associated with each core. Each core maintains and updates the respective bitmap based on the loads of the threads. The multiple bitmaps are maintained in the global memory location which is accessible by a multiple thread domains configured to execute threads using the cores. Execution of the multiple thread domains is balanced using the multiple cores based on loads of each thread described in each bitmap.

Abstract: An apparatus, method, and computer program product are provided for utilizing secondary threads to assist primary threads in performing application tasks. In use, a plurality of primary threads are utilized for performing at least one of a plurality of tasks of an application utilizing at least one corresponding core. Further, it is determined whether the primary threads require assistance in performing one or more of the plurality of tasks of the application. Based on such determination, a plurality of secondary threads are utilized for performing the one or more of the plurality of tasks of the application.