Patents by Inventor Jiacheng LEI

Jiacheng LEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966552
    Abstract: A touch substrate manufacturing method, for manufacturing a target touch substrate to be assembled with a display substrate, is provided. A size of an active display region of the display substrate is a first preset size. The method includes: providing a touch substrate to be processed having a second preset size, the second preset size being greater than the first preset size; and cutting, in at least one cutting direction, the touch substrate to be processed to obtain the target touch substrate, the cutting direction being parallel to an extending direction of a touch channel on the touch substrate to be processed. A manufacturing method for touch module, a touch substrate and a touch module are also provided.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: April 23, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jian Tian, Xintao Wu, Zouming Xu, Chunjian Liu, Jie Lei, Shaoyi Zhan, Jie Wang, Jianying Zhang, Jiacheng Ding
  • Patent number: 11901445
    Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 13, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jiacheng Lei, James Jerry Joseph, Lawrence Selvaraj Susai, Shyue Seng Tan
  • Patent number: 11888051
    Abstract: Structures for a high-electron-mobility transistor and methods of forming a structure for a high-electron-mobility transistor. The high-electron-mobility transistor has a first semiconductor layer, a second semiconductor layer adjoining the first semiconductor layer along an interface, a gate electrode, and a source/drain region. An insulator region is provided in the first semiconductor layer and the second semiconductor layer. The insulator region extends through the interface at a location laterally between the gate electrode and the source/drain region.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: January 30, 2024
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Jiacheng Lei, Lawrence Selvaraj Susai, Joseph James Jerry
  • Patent number: 11444168
    Abstract: A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: September 13, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jiacheng Lei, James Jerry Joseph, Khee Yong Lim, Lulu Peng, Lawrence Selvaraj Susai
  • Patent number: 11380677
    Abstract: According to various embodiments, a transistor device may include a semiconductor structure having a trench formed therein. The semiconductor structure may include a buffer layer and a barrier layer arranged over the buffer layer. The trench may extend at least to the buffer layer. The transistor device may include a source terminal, a drain terminal, and a gate terminal arranged between the source terminal and the drain terminal. The gate terminal may extend into the trench. The transistor device may include an electrode component. The electrode component may include an electrode. The electrode component may extend into the trench where the electrode component is separated from the gate terminal. The electrode component may contact a side wall of the trench.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: July 5, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jiacheng Lei, Lawrence Selvaraj Susai
  • Publication number: 20220157977
    Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Inventors: Jiacheng LEI, James JERRY JOSEPH, Lawrence Selvaraj SUSAI, Shyue Seng TAN
  • Publication number: 20220140096
    Abstract: A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.
    Type: Application
    Filed: November 2, 2020
    Publication date: May 5, 2022
    Inventors: Jiacheng LEI, James JERRY JOSEPH, Khee Yong LIM, Lulu PENG, Lawrence Selvaraj SUSAI
  • Publication number: 20210351286
    Abstract: Structures for a high-electron-mobility transistor and methods of forming a structure for a high-electron-mobility transistor. The high-electron-mobility transistor has a first semiconductor layer, a second semiconductor layer adjoining the first semiconductor layer along an interface, a gate electrode, and a source/drain region. An insulator region is provided in the first semiconductor layer and the second semiconductor layer. The insulator region extends through the interface at a location laterally between the gate electrode and the source/drain region.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Inventors: Jiacheng Lei, Lawrence Selvaraj Susai, Joseph James Jerry
  • Publication number: 20210335778
    Abstract: According to various embodiments, a transistor device may include a semiconductor structure having a trench formed therein. The semiconductor structure may include a buffer layer and a barrier layer arranged over the buffer layer. The trench may extend at least to the buffer layer. The transistor device may include a source terminal, a drain terminal, and a gate terminal arranged between the source terminal and the drain terminal. The gate terminal may extend into the trench. The transistor device may include an electrode component. The electrode component may include an electrode. The electrode component may extend into the trench where the electrode component is separated from the gate terminal. The electrode component may contact a side wall of the trench.
    Type: Application
    Filed: April 28, 2020
    Publication date: October 28, 2021
    Inventors: Jiacheng LEI, Lawrence Selvaraj SUSAI