Abstract: A columnar storage method and a query method and system for time series data. The storage method includes: dividing a column of time series data into a plurality of pages, wherein each page stores a part of data points of the column of time series data and the sum of the data points stored in all the pages is all the data points in the column of time series data (S1); and setting two parts, i.e., a page header and a page body, for each page, storing summary index information of all the data points in the page in the page header of the page and storing data value information of all the data points in the page in the page body of the page (S2).

Abstract: Provided are a capacity expansion method and a capacity expansion system based on a dual-level list structure; a first level list of the dual-level list structure is a first-level array in which at least one array identifier is stored; a second level list of the dual-level list structure includes at least one second-level array, each second-level array stores data to be stored and corresponds to only one array identifier; the method includes: creating a new first-level array when an amount of data stored in the second-level array corresponding to each array identifier reaches a maximum value, a size of a new first-level array being greater than that of a current first-level array, and increasing a number of the second-level arrays; and copying the array identifier stored in the current first-level array to the new first-level array, and replacing the current first-level array with the new first-level array.

Abstract: A columnar storage method and a query method and system for time series data. The storage method includes: dividing a column of time series data into a plurality of pages, wherein each page stores a part of data points of the column of time series data and the sum of the data points stored in all the pages is all the data points in the column of time series data (S1); and setting two parts, i.e., a page header and a page body, for each page, storing summary index information of all the data points in the page in the page header of the page and storing data value information of all the data points in the page in the page body of the page (S2).

Abstract: Provided are a capacity expansion method and a capacity expansion system based on a dual-level list structure; a first level list of the dual-level list structure is a first-level array in which at least one array identifier is stored; a second level list of the dual-level list structure includes at least one second-level array, each second-level array stores data to be stored and corresponds to only one array identifier; the method includes: creating a new first-level array when an amount of data stored in the second-level array corresponding to each array identifier reaches a maximum value, a size of a new first-level array being greater than that of a current first-level array, and increasing a number of the second-level arrays; and copying the array identifier stored in the current first-level array to the new first-level array, and replacing the current first-level array with the new first-level array.

Abstract: A scan-based self-test architecture and method using weighted scan enable signals is disclosed. The self-test architecture comprises: a linear feedback shift register; a phase shifter connected to outputs of the linear feedback shift register, and scan chains and the combinational part of the circuit under test; an AND gate; scan chains, each being formed by serially connecting multiple scan flip-flops having the same architecture; a multiplexer; and a logic unit for generating weighted random signal, whose inputs are connected with the phase shifter; the logic unit randomly selects the input pseudo random signals, weights the selected pseudo random signals, and assigns the weighted pseudo random signals assigned to the scan enable signals of the scan chains, to control the switching of the scan chains between the scan shift mode and the functional mode. The test effectiveness of scan-based BIST can be improved greatly using the test scheme with weighted scan enable signals.

Abstract: A scan-based self-test architecture and method using weighted scan enable signals is disclosed. The self-test architecture comprises: a linear feedback shift register; a phase shifter connected to outputs of the linear feedback shift register, and scan chains and the combinational part of the circuit under test; an AND gate; scan chains, each being formed by serially connecting multiple scan flip-flops having the same architecture; a multiplexer; and a logic unit for generating weighted random signal, whose inputs are connected with the phase shifter; the logic unit randomly selects the input pseudo random signals, weights the selected pseudo random signals, and assigns the weighted pseudo random signals assigned to the scan enable signals of the scan chains, to control the switching of the scan chains between the scan shift mode and the functional mode. The test effectiveness of scan-based BIST can be improved greatly using the test scheme with weighted scan enable signals.

Abstract: A method and apparatus for reducing pin overhead in a non-scan design for testability, The method comprises connecting control signals of test points l1£l2£, . . . , £lh to a first primary input PI1 through AND gate switch, connecting control signals of test points lj, . . . , £lq to a kth primary input PIk through AND gate switch until every test point is connected to one of the primary inputs PI1, PI2, . . . , PIk, connecting a 1-control point to AND gate directly, connecting a 0-control point to AND gate through inverter, sharing one AND gate among all control points that are connected to the same primary input, controlling all control points by an uniform test signal, and checking whether the test points and the primary inputs produce new re-convergent fan-out while reducing inputs of the control signals.

Abstract: A method and apparatus for scan design architecture with non-scan testing cost is disclosed. In one embodiment, the method comprises: transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; connecting said plurality of sequential cells with at least one shifter registers; obtaining at least one scan chains; and substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit. In another embodiment, the apparatus comprises: means for transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; means for connecting said plurality of sequential cells with at least one shifter registers; means for obtaining at least one scan chains; and means for substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit.

Abstract: A method and apparatus for scan design architecture with non-scan testing cost is disclosed. In one embodiment, the method comprises: transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; connecting said plurality of sequential cells with at least one shifter registers; obtaining at least one scan chains; and substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit. In another embodiment, the apparatus comprises: means for transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; means for connecting said plurality of sequential cells with at least one shifter registers; means for obtaining at least one scan chains; and means for substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit.

Abstract: A method and apparatus for reducing pin overhead in a non-scan design for testability is disclosed. In one embodiment, the method comprises: connecting control signals of test points l1, l2, . . . , lh to a first primary input PI1 through AND gate switch, connecting control signals of test points lj, . . . , lq to a second primary input PI2 through AND gate switch until every test point is connected to either primary inputs PI1 or PI2, connecting a 1-control point to AND gate directly, connecting a 0-control point to AND gate through inverter, sharing one AND gate among all control points that are connected to the same primary input, controlling all control points by an uniform signal test, and checking whether the test points and the primary inputs produce new re-convergent fan-out while reducing inputs of the control signals. In another embodiment, the apparatus comprises: means for connecting control signals of test points l1, l2, . . .