Abstract: A method includes receiving an instruction to be executed by a processor. The method further includes performing a lookup in a page crossing buffer that includes one or more entries to determine if the instruction has an entry in the page crossing buffer. Each of the entries includes a physical address. The method further includes, when the page crossing buffer has the entry in the page crossing buffer, retrieving a particular physical address from the entry in the page crossing buffer.

Abstract: Processor access of memory is monitored. The monitoring includes identifying the accesses being to a local memory or a non-local memory. Based on the monitoring, the processor is switched from a non-local memory access mode to a local memory access mode.

Abstract: A method implemented by a central processing unit (CPU), comprising decoding a first instruction word of a first instruction pair, wherein the first instruction word comprises a first operation code identifying a first operation, storing the first operation code in a register memory upon decoding the first instruction word, decoding a second instruction word of the first instruction pair, wherein the second instruction word comprises a first operand, generating a first decoded instruction pair by combining the first operation code stored in the register memory with the first operand in the second instruction word. The method further comprises executing the first decoded instruction pair by performing the first operation on the first operand.

Abstract: The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.

Abstract: An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.

Abstract: Processor access of memory is monitored. The monitoring includes identifying the accesses being to a local memory or a non-local memory. Based on the monitoring, the processor is switched from a non-local memory access mode to a local memory access mode.

Abstract: A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.

Abstract: The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.

Abstract: A system for authorizing an operation is provided. The system may acquire motion data collected by a wearable device. A mobile terminal may determine whether the motion data matches with a physical motion for verification. If the motion data matches with the physical motion for verification, the mobile terminal may be authorized to perform a predetermined operation corresponding to the physical motion for verification. Thus, a user's identity may be verified based on the wearable device that collects motion data.

Abstract: The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.

Abstract: Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.

Abstract: A method for preparing temsirolimus, the method including: using a substituted aromatic aldehyde to protect 2,2-dimethylol propionic acid to produce intermediate II; carrying out reaction between the intermediate II and 2,4,6-trichlorobenzoyl chloride; carrying out condensation reaction between a resulting product and rapamycin to produce intermediate III; and finally using sulfuric acid to remove a protecting group from the intermediate III to yield temsirolimus.

Abstract: The present disclosure provides a method and networking equipment for acquiring feature information. It relates to a field of computer and communication technology to acquire the device information using the networking equipment such as a router and to send the device information to other users. The method may include: receiving a network connection request sent from a first terminal device; acquiring device information of the first terminal device in response to the received network connection request; determining the feature information of the first terminal device based on the acquired device information; and outputting the determined feature information.

Abstract: An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.

Abstract: A method for synthesizing temsirolimus, the method including: using a substituted boric acid to protect 2,2-dimethylol propionic acid to produce intermediate II; carrying out a reaction between the intermediate II and 2,4,6-trichlorobenzoyl chloride; carrying out condensation reaction between a resulting product and rapamycin to produce intermediate III; and finally using a diol to remove a protecting group from the intermediate III to yield temsirolimus.

Abstract: A method includes receiving an instruction to be executed by a processor. The method further includes performing a lookup in a page crossing buffer that includes one or more entries to determine if the instruction has an entry in the page crossing buffer. Each of the entries includes a physical address. The method further includes, when the page crossing buffer has the entry in the page crossing buffer, retrieving a particular physical address from the entry in the page crossing buffer.

Abstract: A method for preparing temsirolimus, the method including: using a substituted aromatic aldehyde to protect 2,2-dimethylol propionic acid to produce intermediate II; carrying out reaction between the intermediate II and 2,4,6-trichlorobenzoyl chloride; carrying out condensation reaction between a resulting product and rapamycin to produce intermediate III; and finally using sulfuric acid to remove a protecting group from the intermediate III to yield temsirolimus.

Abstract: A method for synthesizing temsirolimus, the method including: using a substituted boric acid to protect 2,2-dimethylol propionic acid to produce intermediate II; carrying out a reaction between the intermediate II and 2,4,6-trichlorobenzoyl chloride; carrying out condensation reaction between a resulting product and rapamycin to produce intermediate III; and finally using a diol to remove a protecting group from the intermediate III to yield temsirolimus.