Patents by Inventor Jiajing JIN

Jiajing JIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250252047
    Abstract: Provided are a solid-state drive and a wear leveling method. The solid-state drive includes a plurality of zones, a mapping relationship and an SSD controller. The SSD controller is configured to: determine, according to the mapping relationship, an identifier of a first target zone corresponding to an identifier of a to-be-written zone in response to receiving a data write command from a host drive unit, and write the to-be-written data to the first target zone. The data write command carries the identifier of the to-be-written zone determined by the host drive unit and to-be-written data, the mapping relationship includes an identifier of an alternate zone corresponding to an identifier of each of the plurality of zones, and the alternate zone of each zone is a zone, determined from the plurality of zones, with fewest programmed/erased cycles.
    Type: Application
    Filed: December 27, 2024
    Publication date: August 7, 2025
    Applicant: T-Head (Chengdu) Semiconductor Co., Ltd.
    Inventors: Jiajing Jin, Jiu Heng, Xiang Gao
  • Patent number: 12360702
    Abstract: A solid state drive (SSD) includes an NAND memory and an SSD controller. The SSD controller includes an interface coupled to a host machine, a nonvolatile memory controller coupled to the interface, and a processor coupled to the nonvolatile memory controller. The SSD controller is configured to: receive, via the interface, a write command from the host machine; process, by the nonvolatile memory controller, the write command; transmit, from the nonvolatile memory controller to the processor, a system message; process, by the processor according to Zoned Namespaces (ZNS) protocol, the system message; obtain, by the nonvolatile memory controller via the interface, host data for storage from the host machine; and write the host data to the NAND memory based on a result of processing the system message. Processing the system message by the processor and obtaining the host data by the nonvolatile memory controller are executed in parallel.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: July 15, 2025
    Assignee: T-Head (Shanghai) Semiconductor Co., Ltd.
    Inventors: Yuming Xu, Jiu Heng, Fei Xue, Wentao Wu, Jifeng Wang, Jiajing Jin, Xiang Gao
  • Patent number: 12277341
    Abstract: This application describes systems and methods for facilitating memory access on flash drives. An example method may start with receiving a read command on a flash memory from a host specifying a logic block address (LBA). The flash memory may include a plurality of blocks grouped into a plurality of super blocks, and each of the plurality of blocks may include a plurality of pages. The method may further include determining a zone identification and an LBA offset based on the LBA; determining a flash physical address (FPA) corresponding to the LBA by accessing a mapping table stored in a random access memory (RAM) according to the zone identification and the LBA offset (e.g., the mapping table includes a plurality of FPAs arranged in a plurality of zones corresponding to the plurality of super blocks); and determining a page number and a block identification corresponding to the FPA.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: April 15, 2025
    Assignee: T-Head (Shanghai) Semiconductor Co., Ltd.
    Inventors: Xiang Gao, Fei Xue, Jiajing Jin, Wentao Wu, Jiu Heng, Yuming Xu, Jifeng Wang
  • Patent number: 12141479
    Abstract: This application describes systems and methods for facilitating memory access in flash drives. An example method performed by a memory controller may include receiving, from a host, a write command comprising data to be written into a flash memory; splitting the data into a first portion and a second portion; storing the first portion into a static random-access memory (SRAM) in the memory controller; storing the second portion into a dynamic random-access memory (DRAM) communicatively coupled with the memory controller; initiating a configuration operation corresponding to the write command; fetching the first portion from the SRAM and the second portion from the DRAM in response to the flash translation layer indicating a ready status to store the data into the flash memory; combining the fetched first portion and the fetched second portion; and storing the combined first portion and the second portion into the flash memory.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: November 12, 2024
    Assignee: T-Head (Shanghai) Semiconductor Co., Ltd.
    Inventors: Jifeng Wang, Yuming Xu, Wentao Wu, Fei Xue, Xiang Gao, Jiajing Jin
  • Publication number: 20240176539
    Abstract: This application describes systems and methods for facilitating memory access in flash drives. An example method performed by a memory controller may include receiving, from a host, a write command comprising data to be written into a flash memory; splitting the data into a first portion and a second portion; storing the first portion into a static random-access memory (SRAM) in the memory controller; storing the second portion into a dynamic random-access memory (DRAM) communicatively coupled with the memory controller; initiating a configuration operation corresponding to the write command; fetching the first portion from the SRAM and the second portion from the DRAM in response to the flash translation layer indicating a ready status to store the data into the flash memory; combining the fetched first portion and the fetched second portion; and storing the combined first portion and the second portion into the flash memory.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 30, 2024
    Inventors: Jifeng WANG, Yuming XU, Wentao WU, Fei XUE, Xiang GAO, Jiajing JIN
  • Publication number: 20240143225
    Abstract: A solid state drive (SSD) includes an NAND memory and an SSD controller. The SSD controller includes an interface coupled to a host machine, a nonvolatile memory controller coupled to the interface, and a processor coupled to the nonvolatile memory controller. The SSD controller is configured to: receive, via the interface, a write command from the host machine; process, by the nonvolatile memory controller, the write command; transmit, from the nonvolatile memory controller to the processor, a system message; process, by the processor according to Zoned Namespaces (ZNS) protocol, the system message; obtain, by the nonvolatile memory controller via the interface, host data for storage from the host machine; and write the host data to the NAND memory based on a result of processing the system message. Processing the system message by the processor and obtaining the host data by the nonvolatile memory controller are executed in parallel.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 2, 2024
    Inventors: Yuming XU, Jiu HENG, Fei XUE, Wentao WU, Jifeng WANG, Jiajing JIN, Xiang GAO
  • Publication number: 20240143219
    Abstract: This application describes systems and methods for facilitating memory access on flash drives. An example method may start with receiving a read command on a flash memory from a host specifying a logic block address (LBA). The flash memory may include a plurality of blocks grouped into a plurality of super blocks, and each of the plurality of blocks may include a plurality of pages. The method may further include determining a zone identification and an LBA offset based on the LBA; determining a flash physical address (FPA) corresponding to the LBA by accessing a mapping table stored in a random access memory (RAM) according to the zone identification and the LBA offset (e.g., the mapping table includes a plurality of FPAs arranged in a plurality of zones corresponding to the plurality of super blocks); and determining a page number and a block identification corresponding to the FPA.
    Type: Application
    Filed: February 22, 2023
    Publication date: May 2, 2024
    Inventors: Xiang GAO, Fei XUE, Jiajing JIN, Wentao WU, Jiu HENG, Yuming XU, Jifeng WANG
  • Publication number: 20240118835
    Abstract: An SSD includes an MRAM, an NAND memory, and an SSD controller. The SSD controller is configured to receive first data from a host machine, save the first data to an SSD data buffer, fetch the first data from the SSD data buffer and write the first data to the MRAM via the MRAM controller, determine, by the data allocation circuit based on a characteristic of the first data, whether to save the first data to the MRAM or the NAND memory, and in response to determining saving the first data to the NAND memory, read the first data from the MRAM, write the first data to the NAND memory, and erase the first data from the MRAM.
    Type: Application
    Filed: April 30, 2023
    Publication date: April 11, 2024
    Inventors: Fei XUE, Wentao WU, Jiajing JIN, Xiang GAO, Jifeng WANG, Yuming XU, Jiu HENG, Hongzhong ZHENG