Patents by Inventor Jiajun Fan

Jiajun Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240123331
    Abstract: A method and an electronic device for processing a game signal are provided, the method includes: providing a first operation region in response to an interaction operation acting on a graphical user interface, determining a target signal identifier from the at least one signal identifier in response to a first touch operation acting on the first operation region; providing a second operation region and at least one first game object identifier through the graphical user interface; determining a target game object identifier from the at least one first game object identifier in response to a second touch operation acting on the second operation region; sending a target signal for the target game object identifier according to the target signal identifier in response to an end of the second touch operation.
    Type: Application
    Filed: August 9, 2021
    Publication date: April 18, 2024
    Applicant: NETEASE (HANGZHOU) NETWORK CO., LTD.
    Inventors: Jiajun FAN, Zhaoda HE
  • Publication number: 20240094290
    Abstract: A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Yanhua Yi, Yu Yang, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang
  • Patent number: 11860227
    Abstract: A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: January 2, 2024
    Assignee: Synopsys, Inc.
    Inventors: Yanhua Yi, Yu Yang, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang
  • Publication number: 20230331221
    Abstract: A device control system, method, electronic device, and storage medium are applied within a magnetizing environment such as a Magnetic Resonance environment. The device control system includes a magnetic field detecting module configured to determine a magnetic field intensity at the location of the first device; and/or, a distance determining module configured to determine a distance between the first device and the second device; a monitoring module configured to generate an alarm command according to the magnetic field intensity and/or the distance; and a control module configured to control the first device according to the alarm command.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Applicant: Medcaptain Medical Technology Co., Ltd.
    Inventors: Jiajun FAN, Yuchen WEI, Yaoqi ZHONG
  • Publication number: 20220187367
    Abstract: A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 16, 2022
    Inventors: Yanhua Yi, Yu Yang, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang
  • Publication number: 20180230174
    Abstract: There is described a method of transformation of a cellulosic material, such as, lignocellulosic biomass material and/or cellulose, into a directly fermentable saccharide containing mixture wherein said method of transformation comprises the microwave assisted hydrothermal treatment of the cellulosic material.
    Type: Application
    Filed: January 20, 2016
    Publication date: August 16, 2018
    Applicant: University of York
    Inventors: Vitaliy Budarin, James Hanley Clark, Jiajun Fan, Mark Gronnow