Abstract: Embodiments of semiconductor chips and fabrication methods thereof are disclosed. In one example, a semiconductor chip includes a main chip region and a protection structure surrounding the main chip region in a plan view. The protection structure includes a dielectric layer and a conductive portion in the dielectric layer. The conductive portion includes a conductive layer and a core having a material different from that of the conductive layer.

Abstract: In some implementations, a structure including a carrier wafer, and a first device wafer on the carrier wafer is provided. First ablation structures are formed in the structure. The first ablation structures extend through the first device wafer. A second device wafer is bonded on the first device wafer having the first ablation structures.

Abstract: A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.

Abstract: Embodiments of semiconductor chips and fabrication methods thereof are disclosed. In one example, a semiconductor chip includes a main chip region and a protection structure surrounding the main chip region in a plan view. The protection structure includes a dielectric layer and a conductive portion in the dielectric layer. The conductive portion includes a conductive layer and a core having a material different from that of the conductive layer.

Abstract: A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.

Abstract: Embodiments of 3D memory devices having an inter-deck plug and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck including interleaved conductor and dielectric layers above the substrate, a second memory deck including interleaved conductor and dielectric layers above the first memory deck, and a first and a second channel structure each extending vertically through the first or second memory deck. The first channel structure includes a first memory film and semiconductor channel along a sidewall of the first channel structure, and an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel. A lateral surface of the inter-deck plug is smooth. The second channel structure includes a second memory film and semiconductor channel along a sidewall of the second channel structure. The second semiconductor channel is in contact with the inter-deck plug.

Abstract: Embodiments of 3D memory devices having an inter-deck plug and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck including interleaved conductor and dielectric layers above the substrate, a second memory deck including interleaved conductor and dielectric layers above the first memory deck, and a first and a second channel structure each extending vertically through the first or second memory deck. The first channel structure includes a first memory film and semiconductor channel along a sidewall of the first channel structure, and an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel. A lateral surface of the inter-deck plug is smooth. The second channel structure includes a second memory film and semiconductor channel along a sidewall of the second channel structure. The second semiconductor channel is in contact with the inter-deck plug.

Abstract: Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.

Abstract: Embodiments of 3D memory devices having an inter-deck plug and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck including interleaved conductor and dielectric layers above the substrate, a second memory deck including interleaved conductor and dielectric layers above the first memory deck, and a first and a second channel structure each extending vertically through the first or second memory deck. The first channel structure includes a first memory film and semiconductor channel along a sidewall of the first channel structure, and an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel. A lateral surface of the inter-deck plug is smooth. The second channel structure includes a second memory film and semiconductor channel along a sidewall of the second channel structure. The second semiconductor channel is in contact with the inter-deck plug.

Abstract: Embodiments of 3D memory devices having an inter-deck plug and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck including interleaved conductor and dielectric layers above the substrate, a second memory deck including interleaved conductor and dielectric layers above the first memory deck, and a first and a second channel structure each extending vertically through the first or second memory deck. The first channel structure includes a first memory film and semiconductor channel along a sidewall of the first channel structure, and an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel. A lateral surface of the inter-deck plug is smooth. The second channel structure includes a second memory film and semiconductor channel along a sidewall of the second channel structure. The second semiconductor channel is in contact with the inter-deck plug.

Abstract: Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.