Abstract: The disclosure provides a logical address allocation method, apparatus, electronic device and storage medium. The method includes: receiving a first request sent by a target virtual machine unit, the first request being used for registering a logical address of a submission queue entry of the target virtual machine unit; performing a hash operation based on the first request to obtain a first hash value indicating the submission queue entry; acquiring a target hash table corresponding to the target virtual machine unit, and querying the target hash table based on the first hash value to obtain a target hash bucket to which the first hash value belongs; acquiring, based on a hash bucket identification of the target hash bucket, a target logical address corresponding to the hash bucket identification from currently available logical addresses; and registering the target logical address as a corresponding logical address to generate the submission queue entry.

Abstract: The present application relates to the technical field of batteries, and in particular, to a battery electrode plate, an electrode plate assembly, a battery, and an electrical device. The battery electrode plate of the present application comprises a current collector, at least one surface of the current collector being provided with a first coating area, the first coating area being provided with an active material layer, and the active material layer comprising a first active material layer, a second active material layer, and a third active material layer that are connected sequentially from top to bottom along the height direction of the current collector, wherein the attenuation speed of the active material of the second active material layer is smaller than that of the active material in any one of the first active material layer and the third active material layer.

Abstract: Embodiments of the present application relate to a method, a bridging device, a system and a medium of virtualization processing of a storage device. The method comprises: receiving an initial access request to a virtual disk sent by a virtual machine user; translating the virtual address corresponding to the virtual machine to a first physical address corresponding to a host based on a preconfigured address mapping relationship; translating the virtual access address to a second physical address corresponding to the storage device based on a preconfigured virtual partition mapping relationship; and generating a target access request based on the first physical address and the second physical address, and sending the target access request to the host, so as to cause the host to perform information interaction with the storage device based on the target access request.

Abstract: Embodiments of the present application relate to a method, a bridging device, a system and a medium of virtualization processing of a storage device. The method comprises: receiving an initial access request to a virtual disk sent by a virtual machine user; translating the virtual address corresponding to the virtual machine to a first physical address corresponding to a host based on a preconfigured address mapping relationship; translating the virtual access address to a second physical address corresponding to the storage device based on a preconfigured virtual partition mapping relationship; and generating a target access request based on the first physical address and the second physical address, and sending the target access request to the host, so as to cause the host to perform information interaction with the storage device based on the target access request.

Abstract: The disclosure provides a logical address allocation method, apparatus, electronic device and storage medium. The method includes: receiving a first request sent by a target virtual machine unit, the first request being used for registering a logical address of a submission queue entry of the target virtual machine unit; performing a hash operation based on the first request to obtain a first hash value indicating the submission queue entry; acquiring a target hash table corresponding to the target virtual machine unit, and querying the target hash table based on the first hash value to obtain a target hash bucket to which the first hash value belongs; acquiring, based on a hash bucket identification of the target hash bucket, a target logical address corresponding to the hash bucket identification from currently available logical addresses; and registering the target logical address as a corresponding logical address to generate the submission queue entry.

Abstract: Embodiments of the present disclosure provide a data processing method and apparatus, wherein the data processing method includes: determining a first matrix and a second matrix, and splitting the second matrix into a first preset quantity of matrix blocks; invoking a Montgomery modular multiplication and addition instruction to perform an operation on an element included in the first matrix and an element included in a jth matrix block to obtain a matrix block operation result corresponding to the jth matrix block, and covering the element in the jth matrix block with the matrix block operation result corresponding to the jth matrix block; and increasing j by 1, continuing to perform the above-described step of obtaining the matrix block operation result until j is equal to the first preset quantity so as to obtain a target matrix from the matrix multiplication operation performed on the first matrix and the second matrix.

Abstract: Disclosed is a composite comprising from about 50 wt. % to about 97 wt. % of a thermoplastic resin, wherein the thermoplastic resin comprises a polyester; and from about 3 wt. % to about 15 wt. % of a carbon-based filler, wherein the carbon-based filler has a primary surface area of from about 500 to about 1000 m2/g, wherein the composite exhibits a dielectric constant ?? of between 5 and 30 and a dissipation loss ?? of between 0.5 and 45, measured at frequencies between about 10 and about 120 GHz. A molded sample of the composite exhibits a percent reflected power measured in transmission mode of at least 15% when observed according to a Free Space method at frequencies from about 75 GHz to 110 GHz.

Abstract: Disclosed are an array substrate and a liquid crystal display panel. The array substrate includes a plurality of gate lines and a plurality of data lines. The plurality of gate lines and the plurality of data lines are interleaved to form a plurality of pixel areas, and a pixel electrode is formed in each of the pixel areas. The pixel electrode is connected to a corresponding gate line and a corresponding data line via a thin film transistor. The array substrate further includes a common electrode, which is connected to a first pixel electrode and a second electrode via a thin film transistor. A signal in the first pixel electrode and a signal in the second pixel electrode have opposite polarities. The array substrate realizes automatic adjustment of a common electrode voltage, and corresponding regulators or machines are no longer needed. It is favorable to improvement of productivity and competitiveness of the array substrate and the liquid crystal display panel.

Abstract: A liquid crystal panel and the driving method thereof are disclosed. The liquid crystal panel includes at least one storage electrode, a plurality of scanning lines, a plurality of data lines, and a plurality of pixel areas. Each of the pixel areas includes a pixel electrode, a first TFT and a second TFT. The first TFT drives the corresponding pixel electrode. The gate of the second TFT connects with the previous scanning line, and one of the source and the drain of the second TFT connects to the corresponding pixel electrode within the pixel area, and the other one connects with the storage electrode. In this way, the optimal common voltage is applied to the liquid crystal panel when the liquid crystal panel is in a displaying process, and thus the display performance is guaranteed.

Abstract: A liquid crystal device (LCD) and a flexible circuit board are disclosed. The display panel includes a color film substrate, an array substrate, and a liquid crystal layer between the color film substrate and the array substrate. The flexible circuit board is configured for arranging the driving circuit. before the flexible circuit board is bonded, a common voltage of the color film substrate and the common voltage of the array substrate are disconnected. A voltage of the pixel electrode of the array substrate and the common voltage of the color film substrate are independent signals and are independently controllable to form a predetermined voltage difference for aligning the liquid crystal layer between the array substrate and the color film substrate. As such, the voltage difference for aligning the liquid crystal layer between the color film substrate and the array substrate of the self-adjust Vcom LCD may be formed.

Abstract: Disclosed are an array substrate and a liquid crystal display panel. The array substrate includes a plurality of gate lines and a plurality of data lines. The plurality of gate lines and the plurality of data lines are interleaved to form a plurality of pixel areas, and a pixel electrode is formed in each of the pixel areas. The pixel electrode is connected to a corresponding gate line and a corresponding data line via a thin film transistor. The array substrate further includes a common electrode, which is connected to a first pixel electrode and a second electrode via a thin film transistor. A signal in the first pixel electrode and a signal in the second pixel electrode have opposite polarities. The array substrate realizes automatic adjustment of a common electrode voltage, and corresponding regulators or machines are no longer needed. It is favorable to improvement of productivity and competitiveness of the array substrate and the liquid crystal display panel.

Abstract: The present disclosure discloses a method for manufacturing a HVA pixel electrode and an array substrate. The method comprises: a first metal material is deposited on a substrate, and a first conductive metal layer is formed through etching; a first insulating material and a semiconductor material are deposited on a first conductive metal layer, and an intermediate layer is formed through etching; a second insulating material is deposited on the intermediate layer, and a second conductive metal layer is formed through etching; the second conductive metal layer and an exposed part of the intermediate layer are coated with a second insulating material, and contact holes and a three-dimensional insulating structure are formed through etching; the surface of the insulating structure and the exposed parts of other layers are coated with a transparent conductive material, and a transparent conductive layer is formed through etching. A photomasking procedure is saved, and manufacturing cost is saved.

Abstract: The present disclosure discloses a mask plate, a method of manufacturing a corresponding array substrate, and an array substrate, used in the technical field of liquid crystal displays. The mask plate comprises a non-transparent area and a transparent area. The non-transparent area has an intermediate vertical trunk, an intermediate horizontal trunk, and branches extending from the intermediate vertical trunk and the intermediate horizontal trunk. The intermediate vertical trunk and the intermediate horizontal trunk form certain angles with the branches, respectively. The transparent area has a first transparent portion provided between the branches. The first transparent portion is provided with an optical interference unit, which is used for processing light with a first intensity into light with a second intensity, the first intensity being higher than the second intensity.

Abstract: A liquid crystal panel and the driving method thereof are disclosed. The liquid crystal panel includes at least one storage electrode, a plurality of scanning lines, a plurality of data lines, and a plurality of pixel areas. Each of the pixel areas includes a pixel electrode, a first TFT and a second TFT. The first TFT drives the corresponding pixel electrode. The gate of the second TFT connects with the previous scanning line, and one of the source and the drain of the second TFT connects to the corresponding pixel electrode within the pixel area, and the other one connects with the storage electrode. In this way, the optimal common voltage is applied to the liquid crystal panel when the liquid crystal panel is in a displaying process, and thus the display performance is guaranteed.

Abstract: A liquid crystal device (LCD) and a flexible circuit board are disclosed. The display panel includes a color film substrate, an array substrate, and a liquid crystal layer between the color film substrate and the array substrate. The flexible circuit board is configured for arranging the driving circuit. before the flexible circuit board is bonded, a common voltage of the color film substrate and the common voltage of the array substrate are disconnected. A voltage of the pixel electrode of the array substrate and the common voltage of the color film substrate are independent signals and are independently controllable to form a predetermined voltage difference for aligning the liquid crystal layer between the array substrate and the color film substrate. As such, the voltage difference for aligning the liquid crystal layer between the color film substrate and the array substrate of the self-adjust Vcom LCD may be formed.

Abstract: An array substrate includes a plurality of pixels arranged in a matrix, at least one voltage transmission block arranged in all of pixels or a portion of the pixels, and common voltage wirings. The voltage transmission block is configured for transmitting a grayscale voltage received by a pixel electrode within the pixel where the voltage transmission block is located to the common voltage wirings. A plurality of grayscale voltages transmitted to the common voltage wirings cooperatively forms a common voltage. In addition, a LCD includes the above array substrate is also disclosed. In this way, the optimal common voltage may be obtained such that the display performance is guaranteed.

Abstract: A display panel, a LCD, and a manufacturing method of display panels are disclosed. The display panel includes at least one semiconductor transistor having a control end, an input end, and an output end. One of the input end and the output end receives the common voltage of the array substrate, and the other one connects with the common voltage of the color film substrate. Signals applying to the control end are controlled to connect or disconnect the common voltage of the array substrate and the common voltage of the color film substrate. When the common voltage of the array substrate and the common voltage of the color film substrate are disconnected, the voltage difference for aligning the liquid crystal layer be generated. When they are connected, the common voltage of the array substrate may be transmitted to the color film substrate.

Abstract: A liquid crystal panel and the driving method thereof are disclosed. The liquid crystal panel includes at least one storage electrode, a plurality of scanning lines, a plurality of data lines, and a plurality of pixel areas. Each of the pixel areas includes a pixel electrode, a first TFT and a second TFT. The first TFT drives the corresponding pixel electrode. The gate of the second TFT connects with the previous scanning line, and one of the source and the drain of the second TFT connects to the corresponding pixel electrode within the pixel area, and the other one connects with the storage electrode. In this way, the optimal common voltage is applied to the liquid crystal panel when the liquid crystal panel is in a displaying process, and thus the display performance is guaranteed.

Abstract: A liquid crystal panel and the driving method thereof are disclosed. The liquid crystal panel includes at least one storage electrode, a plurality of scanning lines, a plurality of data lines, and a plurality of pixel areas. Each of the pixel areas includes a pixel electrode, a first TFT and a second TFT. The first TFT drives the corresponding pixel electrode. The gate of the second TFT connects with the previous scanning line, and one of the source and the drain of the second TFT connects to the corresponding pixel electrode within the pixel area, and the other one connects with the storage electrode. In this way, the optimal common voltage is applied to the liquid crystal panel when the liquid crystal panel is in a displaying process, and thus the display performance is guaranteed.

Abstract: The present disclosure discloses a method for manufacturing a HVA pixel electrode and an array substrate. The method comprises: a first metal material is deposited on a substrate, and a first conductive metal layer is formed through etching; a first insulating material and a semiconductor material are deposited on a first conductive metal layer, and an intermediate layer is formed through etching; a second insulating material is deposited on the intermediate layer, and a second conductive metal layer is formed through etching; the second conductive metal layer and an exposed part of the intermediate layer are coated with a second insulating material, and contact holes and a three-dimensional insulating structure are formed through etching; the surface of the insulating structure and the exposed parts of other layers are coated with a transparent conductive material, and a transparent conductive layer is formed through etching. A photomasking procedure is saved, and manufacturing cost is saved.